AM6442: Single Byte transfer to SPI TX using BCDMA

Hi Ti,

I was trying to send single byte of data to SPI using BCDMA but i was getting Transfer Failed error . Created TR 15 descriptor pointing to MCSPI1_CH0_TX as destination address for TRD.

pTr->daddr    = 0x20110138U; 

sequence i was trying is as below:

1) TR intialization:

static void App_udmaTrpdInit(Udma_ChHandle chHandle,
uint32_t chIdx,
uint8_t *trpdMem,
const void *destBuf,
const void *srcBuf,
uint32_t length)
{
CSL_UdmapTR15 *pTr;
uint32_t cqRingNum = Udma_chGetCqRingNum(chHandle);

/* Make TRPD with TR15 TR type */
UdmaUtils_makeTrpdTr15(trpdMem, 1U, cqRingNum);

/* Setup TR */
pTr = UdmaUtils_getTrpdTr15Pointer(trpdMem, 0U);
pTr->flags = CSL_FMK(UDMAP_TR_FLAGS_TYPE, CSL_UDMAP_TR_FLAGS_TYPE_4D_BLOCK_MOVE_REPACKING_INDIRECTION);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_STATIC, 0U);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EOL, CSL_UDMAP_TR_FLAGS_EOL_MATCH_SOL_EOL);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EVENT_SIZE, CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION);
if(0U == chIdx)
{
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0, CSL_UDMAP_TR_FLAGS_TRIGGER_NONE);
}
else
{
/* Set global trigger for channel 1 */
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0, CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0);
}
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0_TYPE, CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1, CSL_UDMAP_TR_FLAGS_TRIGGER_NONE);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1_TYPE, CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_CMD_ID, 0x25U); /* This will come back in TR response */
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_SA_INDIRECT, 0U);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_DA_INDIRECT, 0U);
pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EOP, 1U);
pTr->icnt0 = 1U; //ACNT
pTr->icnt1 = 1U; // BCNT
pTr->icnt2 = 1U; // CCNT
// pTr->icnt3 = 1U;
pTr->dim1 = 1U; //SBIDX should be 4
// pTr->dim2 = (pTr->icnt0 * pTr->icnt1); //SCINDX
// pTr->dim3 = (pTr->icnt0 * pTr->icnt1 * pTr->icnt2);
pTr->addr = (uint64_t) Udma_defaultVirtToPhyFxn(srcBuf, 0U, NULL); // Source Address
pTr->fmtflags = 0x00000000U; /* Linear addressing, 1 byte per elem */
pTr->dicnt0 = 1U; // ACNT
pTr->dicnt1 = 1U; // BCNT
pTr->dicnt2 = 1U; // CCNT
// pTr->dicnt3 = 1U;
pTr->ddim1 = 0U; //DBINDX should be 1
// pTr->ddim2 = (pTr->dicnt0 * pTr->dicnt1); //DCINDX
// pTr->ddim3 = (pTr->dicnt0 * pTr->dicnt1 * pTr->dicnt2);
pTr->daddr = 0x20110138U;  // Destination Address

/* Perform cache writeback */
CacheP_wb(trpdMem, UDMA_TEST_TRPD_SIZE, CacheP_TYPE_ALLD);

return;
}

2)  Queuing and Dequeuing :

trpdMem = &gUdmaTestTrpdMem[0U];
trpdMemPhy = (uint64_t) Udma_defaultVirtToPhyFxn(trpdMem, 0U, NULL);
retVal = Udma_ringQueueRaw(Udma_chGetFqRingHandle(chHandle0), trpdMemPhy);
DebugP_assert(UDMA_SOK == retVal);

while(1)
{
      SPI0_CHCONFG = 0X281523E1; 
      SPI0_CHCNTRL = 0x00000101;  // SPI1_CH0 Channel Enable
      ClockP_usleep(100);
      retVal = Udma_ringDequeueRaw(Udma_chGetCqRingHandle(chHandle0), &pDesc);
      if(UDMA_SOK == retVal)
     {
        /* Check TR response status */
       CacheP_inv(trpdMem, UDMA_TEST_TRPD_SIZE, CacheP_TYPE_ALLD);
       trRespStatus = UdmaUtils_getTrpdTr15Response(trpdMem, 1U, 0U);
       DebugP_assert(CSL_UDMAP_TR_RESPONSE_STATUS_COMPLETE == trRespStatus);
      break;
     }
}

Thanks & Regards
Anjan.