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SK-AM62: LVDS Display not working on am62xx based custom board.

siva nallamalli
Intellectual 800 points
Part Number: SK-AM62
Other Parts Discussed in Thread: AB15

We are working on am62xx based custom board trying to bring up goodix lvds display.  

We are not getting colour bars at boot up (i.e splash screen.)

At boot up we are getting below errors.  

[ 1.233035] [drm] Initialized tidss 1.0.0 20180215 for 30200000.dss on minor 0
[ 1.233219] tidss 30200000.dss: [drm] *ERROR* fbdev: Failed to setup generic emulation (ret=-12)

Need your inputs on how to debug this issue.

  • 0
    TI__Mastermind 38955 points

    Hello,

    I need more information to help you debug here. Please provide what changes you made in SW and the output of the test kmstest.

    Regards,
    Krunal

  • 0 in reply to Krunal Bhargav34
    Intellectual 800 points

    I am build using yocto dunfell & meta-ti at 08.06.00.003 branch. 

    you can check my dts file.   I will add kmstest package to the bsp image and update further.

    // SPDX-License-Identifier: GPL-2.0
/*
 * AM625 SK: https://www.ti.com/lit/zip/sprr448
 *
 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;
#include <dt-bindings/pinctrl/k3.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "ti/k3-am625.dtsi"
#include "k3_am625_aurel.dtsi"
//#include "ti/k3-am62x-sk-common.dtsi"


/ {
	compatible =  "ti,am625-aurel-v0.7", "ti,am625"; //03-Nov-2022
	model = "Aurel-v0.7180723-04"; //platform-mmddyy-revision

	/delete-node/cpu@2; //Disabling 2 CPU cores
	/delete-node/cpu@3;

/*
	wlan_lten: regulator-5 {
		compatible = "regulator-fixed";
		regulator-name = "wlan_lten";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		vin-supply = <&vcc_3v3_sys>;
		gpios = <&exp1 11 GPIO_ACTIVE_LOW>;
	};
	wlan_en: regulator-6 {
		/* OUTPUT of SN74AVC2T244DQMR */
/*		compatible = "regulator-fixed";
		regulator-name = "wlan_en";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		enable-active-high;
		vin-supply = <&wlan_lten>;
		gpios = <&main_gpio0 71 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&wlan_en_pins_default>;
	};
*/
	transceiver1: can-phy0 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
        };


	display {
                                compatible = "microtips,13-101hieb0hf0-s";

                                /*
                                * Note that the OLDI TX 0 transmits the odd set of pixels
                                * while the OLDI TX 1 transmits the even set. This is a
                                * fixed configuration in the IP integration and is not
                                * changeable. The properties, "dual-lvds-odd-pixels" and
                                * "dual-lvds-even-pixels" have been used to merely
                                * identify if a Dual Link configuration is required.
                                * Swapping them will not make any difference.
                                */
                                port@0 {
                                        dual-lvds-odd-pixels;
                                        lcd_in0: endpoint {
                                                remote-endpoint = <&oldi_out0>;
                                        };
                                };

                                port@1 {
                                        dual-lvds-even-pixels;
                                        lcd_in1: endpoint {
                                                remote-endpoint = <&oldi_out1>;
                                        };
                                };

	};

//		watchdog: watchdog {
//	        /* TPS3431 */
//	        compatible = "linux,wdt-gpio";        
//	        gpios = <&main_gpio1 45 GPIO_ACTIVE_LOW>;        
//	        hw_algo = "toggle";
	        /* mGaik -> Keep this only if watchdog timer cannot be disabled and you want driver to keep toggling the signal without a APP. */
//        	always-running;         
	        /* mGaik -> CAP at CWD input of TPS3431 is at 470nF making Reset timeout at 36.433 Sec */
	        /* Ideal 36433, but we pet at 36000 mSec rate bit faster than time out, this ensure if we cross 36000 then we do see WDT trigger in */
//	        hw_margin_ms = <36000>; //36-Sec
//	        status = "okay";   
//		};

};

&mcu_pmx0 {
	mcu_i2c0_pins_default: mcu-i2c0-pins-default {
		pinctrl-single,pins = <
			AM62X_MCU_IOPAD(0x044, PIN_INPUT_PULLUP, 0) 	/* (A8) MCU_I2C0_SCL */
			AM62X_MCU_IOPAD(0x048, PIN_INPUT_PULLUP, 0) 	/* (D10) MCU_I2C0_SDA */
		>;
	};

	mcu_mcan1_pins_default: mcu_mcan0_pins_default {
		pinctrl-single,pins = <
			AM62X_MCU_IOPAD(0x0038, PIN_INPUT, 0)  /* (B3) MCU_MCAN0_RX */
			AM62X_MCU_IOPAD(0x0034, PIN_OUTPUT, 0) /* (D6) MCU_MCAN0_TX */
		>;
	};
};

&main_pmx0 {

	wlan_en_pins_default: wlan-en-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x124, PIN_OUTPUT, 7) /* (A23) MMC2_SDCD.GPIO0_71 */
		>;
	};

	main_mmc2_pins_default: main-mmc2-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x120, PIN_INPUT, 0) /* (C24) MMC2_CMD */
			AM62X_IOPAD(0x118, PIN_INPUT, 0) /* (D25) MMC2_CLK */
			AM62X_IOPAD(0x114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */
			AM62X_IOPAD(0x110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */
			AM62X_IOPAD(0x10c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */
			AM62X_IOPAD(0x108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */
			AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */
		>;
	};

	main_wlirq_pins_default: main-wlirq-pins-default {
		pinctrl-single,pins = <
			AM62X_IOPAD(0x128, PIN_INPUT, 7) /* (B23) MMC2_SDWP.GPIO0_72 */
		>;
	};

	main_mcan0_pins_default: main-mcan0-pins-default {
                pinctrl-single,pins = <
                        AM62X_IOPAD(0x1dc, PIN_INPUT, 0) /* (E15) MCAN0_RX */
                        AM62X_IOPAD(0x1d8, PIN_OUTPUT, 0) /* (C15) MCAN0_TX */
                >;
        };

	main_spi2_pins_default: main-spi2-pins-default {
                pinctrl-single,pins = <
          		AM62X_IOPAD(0x1B0, PIN_OUTPUT, 1)   /* (A20) SPI2_CLK pins  on expansion Header*/
            		AM62X_IOPAD(0x1AC, PIN_OUTPUT, 1)  /* (E19) SPI2_CS0 pins on expansion Header */
            		AM62X_IOPAD(0x194, PIN_OUTPUT, 1)   /* (B19) SPI2_D0 pins on expansion Header */
            		AM62X_IOPAD(0x198, PIN_INPUT, 1)   /* (A19) SPI2_D1 pins on expansion Header */
                >;
        };

       main_oldi0_pins_default: main-oldi0-pins-default {
                pinctrl-single,pins = <
                        AM62X_IOPAD(0x0260, PIN_OUTPUT, 0) /* (AA5) OLDI0_A0N */
                        AM62X_IOPAD(0x025c, PIN_OUTPUT, 0) /* (Y6) OLDI0_A0P */
                        AM62X_IOPAD(0x0268, PIN_OUTPUT, 0) /* (AD3) OLDI0_A1N */
                        AM62X_IOPAD(0x0264, PIN_OUTPUT, 0) /* (AB4) OLDI0_A1P */
                        AM62X_IOPAD(0x0270, PIN_OUTPUT, 0) /* (Y8) OLDI0_A2N */
                        AM62X_IOPAD(0x026c, PIN_OUTPUT, 0) /* (AA8) OLDI0_A2P */
                        AM62X_IOPAD(0x0278, PIN_OUTPUT, 0) /* (AB6) OLDI0_A3N */
                        AM62X_IOPAD(0x0274, PIN_OUTPUT, 0) /* (AA7) OLDI0_A3P */
                        AM62X_IOPAD(0x0280, PIN_OUTPUT, 0) /* (AC6) OLDI0_A4N */
                        AM62X_IOPAD(0x027c, PIN_OUTPUT, 0) /* (AC5) OLDI0_A4P */
                        AM62X_IOPAD(0x0288, PIN_OUTPUT, 0) /* (AE5) OLDI0_A5N */
                        AM62X_IOPAD(0x0284, PIN_OUTPUT, 0) /* (AD6) OLDI0_A5P */
                        AM62X_IOPAD(0x0290, PIN_OUTPUT, 0) /* (AE6) OLDI0_A6N */
                        AM62X_IOPAD(0x028c, PIN_OUTPUT, 0) /* (AD7) OLDI0_A6P */
                        AM62X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AD8) OLDI0_A7N */
                        AM62X_IOPAD(0x0294, PIN_OUTPUT, 0) /* (AE7) OLDI0_A7P */
                        AM62X_IOPAD(0x02a0, PIN_OUTPUT, 0) /* (AD4) OLDI0_CLK0N */
                        AM62X_IOPAD(0x029c, PIN_OUTPUT, 0) /* (AE3) OLDI0_CLK0P */
                        AM62X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (AE4) OLDI0_CLK1N */
                        AM62X_IOPAD(0x02a4, PIN_OUTPUT, 0) /* (AD5) OLDI0_CLK1P */
                >;
	};
};


&main_mcan0 {
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&main_mcan0_pins_default>;
        phys = <&transceiver1>;
};

&mcu_i2c0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_i2c0_pins_default>;
	clock-frequency = <400000>;

	bq32000: rtc@68 {
               compatible = "ti,bq32000";
               trickle-resistor-ohms = <1120>;
               reg = <0x68>;
       };

};

&main_i2c1 {

	status = "okay";
	gt928@5d {
        	compatible = "goodix,gt928";
        	reg = <0x5d>;
        	interrupt-parent = <&main_gpio1>;
                interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
        	reset-gpios = <&main_gpio0 54 GPIO_ACTIVE_LOW>;
      };	
};

&main_spi2{
    pinctrl-names = "default";
    pinctrl-0 = <&main_spi2_pins_default>;
    status = "okay";
    //pindir-d0-out-d1-in=1;

    adc@0 {
            compatible = "ti,adc128s052";
            reg = <0>;
            vref-supply = <&vcc_3v3_sys>;
            spi-max-frequency = <1000000>;
            #io-channel-cells = <1>;
    };
};


&dss {
        pinctrl-names = "default";
        pinctrl-0 = <&main_oldi0_pins_default &main_dss0_pins_default>;
};

&dss_ports {
        #address-cells = <1>;
        #size-cells = <0>;

        /* VP1: LVDS Output (OLDI TX 0) */
        port@0 {
                reg = <0>;
                oldi_out0: endpoint {
                        remote-endpoint = <&lcd_in0>;
                };
        };

        /* VP1: LVDS Output (OLDI TX 1) */
        port@2 {
                reg = <2>;
                oldi_out1: endpoint {
                        remote-endpoint = <&lcd_in1>;
                };
        };
};



  • 0 in reply to siva nallamalli
    Intellectual 800 points

    I need to add  meta-arago-distro to my bblayers.conf. 

                           meta-qt5 to my bblayers.conf.

    We are on meta-qt6. 

    I need to do above changes for adding kmstest to our bsp. I included kms++ package to my IMAGE_INSTALL.

    Here is the output of kmsttest

    root@Node3408e17e8eb5:~# kmstest
    terminate called after throwing an instance of 'std::invalid_argument'
    what(): DRM_IOCTL_MODE_CREATE_DUMB failed: Cannot allocate memory
    Aborted. 

  • 0 in reply to siva nallamalli
    TI__Mastermind 38955 points

    Hello,

    How much RAM do you have on your custom board? The following error "what(): DRM_IOCTL_MODE_CREATE_DUMB failed: Cannot allocate memory" seems to imply that either CMA is not configured or not enough CMA left for DSS to run.

    Regards,
    Krunal

  • 0 in reply to Krunal Bhargav34
    Intellectual 800 points

    Our Custom board is having 512MB RAM.

  • 0 in reply to siva nallamalli
    TI__Mastermind 38955 points

    Hello,

    Okay. How much CMA have you allocated and in your dmesg logs, do you see any errors related to CMA failed to allocate? 

    Regards,
    Krunal 

  • 0 in reply to Krunal Bhargav34
    Intellectual 800 points

    I am getting this error at boot up.

    cma: Failed to reserve 512 MiB.

    I fallowed below url where i can set CMA size from u-boot command setenv args_all $args_all cma=24M.

    software-dl.ti.com/.../Foundational_Components_Multimedia_wave5.html

    with CMA size as 24M, i am not seeing any drm/cma errors at bootup.

    Here is the output of kmstest. with kmstest i can see colour bars on LCD.


    root@Node3408e17e8eb5:~# kmstest
    Connector 0/@39: LVDS-1
    Crtc 0/@37: 1920x1200 161.325 1920/12/128/20/? 1200/20/19/4/? 62 (62.40) 0 0x48
    Plane 0/@31: 0,0-1920x1200
    Fb 47 1920x1200-XR24
    press enter to exit

    root@Node3408e17e8eb5:~# kmsprint
    Connector 0 (39) LVDS-1 (connected)
    Encoder 0 (38) LVDS
    Crtc 0 (37) 1920x1200 161.325 1920/12/128/20 1200/20/19/4 62 (62.40)
    Plane 0 (31) fb-id: 46 (crtcs: 0) 0,0 1920x1200 -> 0,0 1920x1200 (AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 XR15 XB15)
    FB 46 1920x1200

    I just want to know who to fix this CMA memory size value, is there any calculation, min & max values, thresholds.

  • +1 in reply to siva nallamalli
    TI__Mastermind 38955 points

    Hello,

    At minimum I would recommend 20MB because of the render buffer (1920x1200x4(bytes/pixel)x2(front/back buffers). However, it will be very application specific and you will need to optimize the CMA based on your end application. For example, if you are doing high end rendering, analytics or ARM compute, you may need to review the free memory and adjust CMA accordingly. 

    Regards,
    Krunal