Hi,
I am using am3354 with processor SDK 06.01.00.08.
When the UART receives data, it may add an incorrect byte of data.
I referred to this page (software-dl.ti.com/.../UART.html).
I ran a test using the serialcheck command. That test can fail.serialcheck -d /dev/ttyS1 -f binary -m r -l 100000 -b 115200 | tee RS232C_$(date +"%Y%m%d%H%M").log &
sleep 2
serialcheck -d /dev/ttyS1 -f binary -m t -l 100000 -b 115200 &
sleep 2
serialcheck -d /dev/ttyS2 -f binary -m r -l 100000 -h -b 115200 | tee RS422_$(date +"%Y%m%d%H%M").log &
sleep 2
serialcheck -d /dev/ttyS2 -f binary -m t -l 100000 -h -b 115200 &
ttyS1(as RS232C) and ttyS2 (as RS422) used for testing are looped back.
One of the results is below.
MNeeded 43 reads 0 writes Oh oh, inconsistency at pos 3280 (0xcd0). Original sample: 00000ca0: f8 a8 ac 2e 6c b1 ce 60 30 32 5e 4c 83 f8 eb 04 ....l..`02^L.... 00000cb0: 1a 17 0e 03 bb 84 b5 a9 ea a7 78 40 3a 07 16 29 ..........x@:..) 00000cc0: cf 8e 95 93 3b f0 54 91 64 c7 3b 2c 51 8f ae a2 ....;.T.d.;,Q... 00000cd0: b0 ef fd a7 e3 f6 28 9e d6 d1 8f eb 5a 13 6b 46 ......(.....Z.kF 00000ce0: 21 67 3b 32 6f 5d f6 91 fd 8d c9 9d 4b aa 9a d2 !g;2o]......K... 00000cf0: 47 16 b6 3f 9a 1a e7 52 83 1c 8a 0c a4 1f 0f 83 G..?...R........ Received sample: 00000ca0: f8 a8 ac 2e 6c b1 ce 60 30 32 5e 4c 83 f8 eb 04 ....l..`02^L.... 00000cb0: 1a 17 0e 03 bb 84 b5 a9 ea a7 78 40 3a 07 16 29 ..........x@:..) 00000cc0: cf 8e 95 93 3b f0 54 91 64 c7 3b 2c 51 8f ae a2 ....;.T.d.;,Q... 00000cd0: 3e b0 ef fd a7 e3 f6 28 9e d6 d1 8f eb 5a 13 6b >......(.....Z.k 00000ce0: 46 21 67 3b 32 6f 5d f6 91 fd 8d c9 9d 4b aa 9a F!g;2o]......K.. 00000cf0: d2 47 16 b6 3f 9a 1a e7 52 83 1c 8a 0c a4 1f 0f .G..?...R....... loops 3534 / 100000[K cts: 0 dsr: 0 rng: 0 dcd: 0 rx: 14475266 tx: 14475264 frame 0 ovr 0 par: 0 brk: 0 buf_ovrr: 0
The results show that the UART-RX rarely inserts random data ("3e" in this case, "7f" or "dc" in other cases, etc.) into the received data.
I thought there might be a problem with the device driver, so I selected the following patch from the latest kernel and applied the patch, but it had no effect.
serial: 8250_omap: Avoid FIFO corruption caused by MDR1 access
git.ti.com/.../tty
serial: 8250_omap: remove wait loop from Errata i202 workaround
git.ti.com/.../tty
serial: 8250_dma: Fix DMA Rx completion race
git.ti.com/.../tty
serial: 8250_dma: Fix DMA Rx rearm race
git.ti.com/.../tty
serial: 8250: Flush DMA Rx on RLSI
git.ti.com/.../tty
serial: 8250: Fall back to non-DMA Rx if IIR_RDI occurs
git.ti.com/.../tty
tty: Fix data race between tiocsti() and flush_to_ldisc()
git.ti.com/.../tty
Is there any way to resolve this?
Regards,
Takayuki.
