TDA4VL-Q1: UDMA cannot capture data

Hi Vinter,

If you are getting interrupt, the issue is most likely not due to GPIO. Can you please check if GTC timer is running? Because if it isn't, then the data will all be 0.

Regards,

Brijesh

Hi, Brijesh
After calling the 'Udma_chResume()' API, I added a statement to print a timestamp, which is variable, meaning that GTC is normal.
Are there any other possible investigation directions?

The following are the current settings related to gpio interrupts. Could you please help confirm again if the settings are correct on TDA4VL MCU 2-1?
uint32_t INTR_OFFSET = 0u;
#define GPIOMUX_INTRTR0_OUTP_START_R5FSS0 (4u + INTR_OFFSET)
static volatile uint32_t gIntAggrLeviEvtId[16] = {
68, 69, 70, 71, 72, 73, 74, 75,
76, 77, 78, 79, 80, 81, 82, 83};

ok, let me check if there is anything else required on TDA4VL. 

Hi，Brijesh
Ok, thank you. Looking forward to your reply.
Also, let me add the sdk information we are using: tda4vl (j721s2) sdk8.04 (Linux&rtos)

Hi, Brijesh

What is the verification result on tda4vl? Do it require any other modifications on tda4vl?

Hi, Brijesh

What is the verification result on tda4vl? Do it require any other modifications on tda4vl?

Additionally, when I read the "GPIO_INTSTAT" register, the corresponding GPIO interrupt bit is 1. Does it mean that GPIO has triggered an interrupt? It can prove that there is no problem with GPIO interrupt configuration, right?

Hi Vinter,

Well, the verification method is to capture timestamp between two entries in the captured array. Lets say if we toggle the GPIO interrupt at every 10ms, then the difference between them should approximately around 10ms. 

Yes, if the INTSTAT register is set, then GPIO is generating interrupt. 

I guess you are also getting the DMA completion interrupt, isn't it? If this is the case, then DMA is also completing, but somehow it is not reading timestamp correctly from the GTC timer. Can you please check if GTC timer is running fine? 

Regards,

Brijesh

Hi, Brijesh

1. 

Brijesh Jadav said:

I guess you are also getting the DMA completion interrupt, isn't it?

I called the following code, so I won't receive a DMA completion interrupt;

CSL_udmapCppi5TrSetReload((CSL_UdmapCppi5TRPD*)pTrpd, 0x1FF, 0U);

I will read data every other period of time, but the interval is set too long and I cannot get the data.

2.

Brijesh Jadav said:

Can you please check if GTC timer is running fine? 

This has been verified and the verification results have been provided to you.

Vinter said:

Hi, Brijesh
After calling the 'Udma_chResume()' API, I added a statement to print a timestamp, which is variable, meaning that GTC is normal.

3. 

Last week, you said you were going to verify on TDA4VL. What was the result of your verification?

Brijesh Jadav said:

ok, let me check if there is anything else required on TDA4VL. 

Hi Vinter,

Vinter said:

Last week, you said you were going to verify on TDA4VL. What was the result of your verification?

I have not got the chance to verify this on EVM, will do it on next few days. 

Vinter said:

CSL_udmapCppi5TrSetReload((CSL_UdmapCppi5TRPD*)pTrpd, 0x1FF, 0U);

I will read data every other period of time, but the interval is set too long and I cannot get the data.

I will first suggest to remove this and get the UDMA completion interrupt to verify that entire path is correctly established. 

Regards,

Brijesh

Hi, Brijesh

Brijesh Jadav said:

I have not got the chance to verify this on EVM, will do it on next few days. 

Ok, looking forward to your verification results. Thank you~!

Brijesh Jadav said:

I will first suggest to remove this and get the UDMA completion interrupt to verify that entire path is correctly established. 

Ok, I'll try to verify it.

However, this part of the code is the same as the code on tda4vm.

Hi Vinter,

What i am suspecting is, GPIOMUX output 16 to 31 are connected to Intg_L2G, but this GPIOMUX outputs are not allocated to R5F in sysconfig. 

We would first need to allocate these GPIOMUX output to R5F and then can use this file. Can you try to reallocate GPIOMUx output 16 to 31 to R5F and then try this code?

Regards,

Brijesh

Hi Vinter,

Even after changing this in the RM, it does not seem to be working. May be some more changes required in L2G register configuration. I will have to check with the HW team.

Regards,

Brijesh 

Hi, Brijesh

1.
I have ported the demo in the following link to TDA4VL and tested it:
e2e.ti.com/.../faq-tda4vm-gpio-dma-trigger-in-tda4-and-test-in-sdk7-1
The main modifications of the demo include:
1）
Change
uint32_t INTR_OFFSET = 8u;
#define GPIOMUX_INTRTR0_OUTP_START_R5FSS0 (16u + INTR_OFFSET)
To：
uint32_t INTR_OFFSET = 0u;
#define GPIOMUX_INTRTR0_OUTP_START_R5FSS0 (4u + INTR_OFFSET)

2）We used gpio on our own board, so we modified the gpio configuration.

3）Since only one DMA blockcpy was used, RM did not make any modifications and used the default RM parameters of sdk;

2. About your testing:

Brijesh Jadav said:

What i am suspecting is, GPIOMUX output 16 to 31 are connected to Intg_L2G, but this GPIOMUX outputs are not allocated to R5F in sysconfig. 

We would first need to allocate these GPIOMUX output to R5F and then can use this file. Can you try to reallocate GPIOMUx output 16 to 31 to R5F and then try this code?

Brijesh Jadav said:

Even after changing this in the RM, it does not seem to be working.

==>> Can you tell me where to modify it in RM? And what is the modification method?

Brijesh Jadav said:

May be some more changes required in L2G register configuration. I will have to check with the HW team.

==>> Ok, waiting for your final confirmation.

You can refer to below faq for allocating or for changing resource allocation.

(99+) [FAQ] TDA4VM: Workflow and Resource allocation build flow for SysConfig Tool? - Processors forum - Processors - TI E2E support forums

Regards,

Brijesh

Hi Vinter,

What all GPIOs are you using? Can you please share you array of gpio_input ? 

Regards,

Brijesh

Hi, Brijesh

The following is the input gpio I am currently using. However, in the "app_gpio_dma. c" demo, I only used AA28 (GPIO0_33).
#define FRS_I 41//T23 GPIO0_41
#define FLS_I 35//T25 GPIO0_35
#define RRS_I 46//AA24 GPIO0_46
#define RLS_I 38//V25 GPIO0_38

#define FLC_I 33//AA28 GPIO0_33
#define FRM_I 39//T24 GPIO0_39
#define FRC_I 42//U24 GPIO0_42
#define FLM_I 36//W24 GPIO0_36

#define RLC_I 34//AD27 GPIO0_34
#define RRM_I 40//AB25 GPIO0_40
#define RRC_I 43//AC25 GPIO0_43
#define RLM_I 37//AA25 GPIO0_37

Hi Vinter,

Can you please share your complete code? It would then be easier. 

Regards,

Brijesh

Hi, Brijesh

Ok, the modified 'app_gpio_dma. c' demo code.(It runs on mcu2-1)

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#include <stdio.h>
#include <string.h>
//#include <xdc/runtime/Error.h>
//#include <ti/sysbios/BIOS.h>
//#include <ti/sysbios/knl/Task.h>

#include <ti/board/board.h>
#include <ti/drv/gpio/GPIO.h>
#include <ti/drv/gpio/soc/GPIO_soc.h>
#include <ti/drv/gpio/src/v0/GPIO_v0.h>
#include <ti/csl/soc/j721s2/src/cslr_soc_baseaddress.h>
#include <ti/csl/src/ip/gpio/V0/gpio.h>

#include <ti/csl/csl_intr_router.h> /* CSL for interrupt router */
#include <ti/osal/osal.h>
#include <ti/drv/sciclient/sciclient.h>
#include <ti/csl/soc/j721s2/src/cslr_main_ctrl_mmr.h>
#include <ti/csl/soc/j721s2/src/cslr_soc_baseaddress.h>

#include <utils/sciclient/include/app_sciclient_wrapper_api.h>

#include <utils/mem/include/app_mem.h>
#include <ti/drv/udma/udma.h>

#include <utils/udma/include/app_udma.h>

#include <platform/j721s2/rtos/mcu2_1/ultrasonic/snr_gpio.h>

/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */

/* Test application stack size */
#define APP_TSK_STACK_MAIN              (16U * 1024U)

/*
 * Application test parameters
 */

#define APP_TIME_READ_CNT     (200U)

/** \brief Number of bytes to copy and buffer allocation */
#define APP_NUM_BYTES         (8U * APP_TIME_READ_CNT)
/** \brief This ensures every channel memory is aligned */
#define APP_BUF_SIZE_ALIGN    ((APP_NUM_BYTES + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
/** \brief Number of channels */
#define APP_NUM_CH            (1U)

/*
 * Ring parameters
 */
/** \brief Number of ring entries - we can prime this much memcpy operations */
#define APP_RING_ENTRIES      (3U)
/** \brief Size (in bytes) of each ring entry (Size of pointer - 64-bit) */
#define APP_RING_ENTRY_SIZE   (sizeof(uint64_t))
/** \brief Total ring memory */
#define APP_RING_MEM_SIZE     (APP_RING_ENTRIES * \
                                         APP_RING_ENTRY_SIZE)
/** \brief This ensures every channel memory is aligned */
#define APP_RING_MEM_SIZE_ALIGN ((APP_RING_MEM_SIZE + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
/**
 *  \brief UDMA TR packet descriptor memory.
 *  This contains the CSL_UdmapCppi5TRPD + Padding to sizeof(CSL_UdmapTR15) +
 *  one Type_15 TR (CSL_UdmapTR15) + one TR response of 4 bytes.
 *  Since CSL_UdmapCppi5TRPD is less than CSL_UdmapTR15, size is just two times
 *  CSL_UdmapTR15 for alignment.
 */
#define APP_TRPD_SIZE         ((sizeof(CSL_UdmapTR15) * 2U) + 4U)
/** \brief This ensures every channel memory is aligned */
#define APP_TRPD_SIZE_ALIGN   ((APP_TRPD_SIZE + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))


#define TRIGGER_TYPE          (CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0)

//uint32_t INTR_OFFSET = 8u;
uint32_t INTR_OFFSET = 0u;

//#define GPIOMUX_INTRTR0_OUTP_START_R5FSS0 (16u + INTR_OFFSET)
#define GPIOMUX_INTRTR0_OUTP_START_R5FSS0 (4u + INTR_OFFSET)

#define GPIO_START            (37)

#define GTC_TIME_ADDR         (0xA90008u)
volatile unsigned long long test_readBackData[50] = {0};

uint8_t gpio_input[APP_NUM_CH] = {
	FLC_I,  FRM_I, FLM_I, FRC_I,
	RLC_I,  RRM_I, RLM_I, RRC_I,
	FRS_I,  RRS_I, FLS_I, RLS_I,
};

uint32_t gpio_output[] = {
	FLC_O, FLM_O, FRM_O, FRC_O,
	RLC_O, RLM_O, RRM_O, RRC_O,
	FRS_O, RRS_O, FLS_O, RLS_O,
};
/* ========================================================================== */
/*                         Structure Declarations                             */
/* ========================================================================== */

typedef struct
{
    int32_t                 chIdx;

    struct Udma_ChObj       chObj;
    struct Udma_EventObj    cqEventObj;
    struct Udma_EventObj    tdCqEventObj;

    Udma_ChHandle           chHandle;
    Udma_EventHandle        cqEventHandle;
    Udma_EventHandle        tdCqEventHandle;

    Udma_DrvHandle          drvHandle;
    SemaphoreP_Handle       transferDoneSem;
    /**< Semaphore to indicate transfer completion */

    uint8_t                 *txRingMem;
    uint8_t                 *txCompRingMem;
    uint8_t                 *txTdCompRingMem;
    uint8_t                 *trpdMem;

    uint64_t                trpd_mem_phy;
    /**< Allocated TRPD memory physical pointer */

    uint8_t                 *destBuf;
} App_ChObj;

typedef struct
{
    Udma_DrvHandle          drvHandle;
    App_ChObj               appChObj[APP_NUM_CH];
} App_Obj;

/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */

static int32_t App_GpioDmaTest(void);

static int32_t App_gpioTriggerTest(App_Obj *appObj, uint32_t inst);

static void App_eventDmaCb(Udma_EventHandle eventHandle,
                           uint32_t eventType,
                           void *appData);
static void App_eventTdCb(Udma_EventHandle eventHandle,
                          uint32_t eventType,
                          void *appData);

static int32_t App_init(App_Obj *appObj);
static int32_t App_deinit(App_Obj *appObj);

static int32_t App_create(App_Obj *appObj);
static int32_t App_delete(App_Obj *appObj);

static void App_trpdInit(App_ChObj *appChObj, uint32_t inst);

static void App_print(const char *str);

static void App_setupPinmux();
static uint32_t Udma_chGetTriggerEvent_2(Udma_DrvHandle drvHandle,
                                       Udma_ChHandle chHandle,
                                       uint32_t trigger);
static void App_setupL2G(App_Obj *appObj, uint32_t enable);
static void App_setUdmaIntAMap(App_Obj *appObj, uint32_t localEvtIdx, uint32_t glblEvt, uint32_t enable);
static void App_initGpio();
static void App_setupGpioMuxIr();
static void App_triggerGpio();

static void App_cacheInv(const void * addr, int32_t size);
static void App_cacheWb(const void *addr, int32_t size);

static int32_t App_pause(App_Obj *appObj);
static int32_t App_resume(App_Obj *appObj);

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

/*
 * UDMA driver and channel objects
 */
App_Obj gAppObj;

#if 0
/*
 * UDMA Memories
 */
static uint8_t gTxRingMem[APP_NUM_CH][APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
static uint8_t gTxCompRingMem[APP_NUM_CH][APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
static uint8_t gTxTdCompRingMem[APP_NUM_CH][APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
static uint8_t gUdmaTrpdMem[APP_NUM_CH][APP_TRPD_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
#endif

#if 0
/*
 * Application Buffers
 */
static uint8_t gUdmaTestSrcBuf[APP_NUM_CH][APP_BUF_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
static uint8_t gUdmaTestDestBuf[APP_NUM_CH][APP_BUF_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
#endif

/* Global test pass/fail flag */
static volatile int32_t gUdmaAppResult = UDMA_SOK;

static volatile uint32_t gIntAggrLeviEvtId[16] = {
        68, 69, 70, 71, 72, 73, 74, 75,
        76, 77, 78, 79, 80, 81, 82, 83};

/* Test application stack */
//static uint8_t  gAppTskStackMain[APP_TSK_STACK_MAIN] __attribute__((aligned(32)));;

/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */

static int32_t App_GpioDmaTest(void)
{
    int32_t     retVal;
    App_Obj    *appObj = &gAppObj;

    retVal = App_init(appObj);
    if(UDMA_SOK != retVal)
    {
        App_print("[Error] UDMA App init failed!!\n");
    }

    App_print("Application started...\n");

    if(UDMA_SOK == retVal)
    {
        retVal = App_create(appObj);
        if(UDMA_SOK != retVal)
        {
            App_print("[Error] UDMA App create failed!!\n");
        }
    }

    if(UDMA_SOK == retVal)
    {
        retVal = App_gpioTriggerTest(appObj, 0);
        if(UDMA_SOK != retVal)
        {
            App_print("[Error] UDMA App test failed!!\n");
        }
    }

    retVal += App_delete(appObj);
    if(UDMA_SOK != retVal)
    {
        App_print("[Error] UDMA App delete failed!!\n");
    }

    retVal += App_deinit(appObj);
    if(UDMA_SOK != retVal)
    {
        App_print("[Error] UDMA App deinit failed!!\n");
    }

    if((UDMA_SOK == retVal) && (UDMA_SOK == gUdmaAppResult))
    {
        App_print("Passed!!\n");
        App_print("All tests have passed!!\n");
    }
    else
    {
        App_print("Failed!!\n");
        App_print("Some tests have failed!!\n");
    }

 	if(UDMA_SOK == gUdmaAppResult)
 		 App_print("gUdmaAppResult == UDMA_SOK!!\n");
	else
		App_print("gUdmaAppResult == UDMA_EFAIL!!\n");
	
    return (0);
}

static int32_t App_gpioTriggerTest(App_Obj *appObj, uint32_t inst)
{
    int32_t         retVal = UDMA_SOK;
    int32_t         chIdx;
    App_ChObj      *appChObj;
    uint32_t        i,j,index1,index2,readback_index;
    uint8_t        *destBuf;
    Udma_ChHandle   chHandle;
    //uint64_t        pDesc = 0;
    //uint32_t       *pTrResp, trRespStatus;

    /* Reset dest buffers */
    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        appChObj = &appObj->appChObj[chIdx];
        chHandle = appChObj->chHandle;
        destBuf  = appChObj->destBuf;

        for(i = 0U; i < APP_NUM_BYTES; i++)
        {
            destBuf[i] = 0U;
        }
        /* Writeback destination buffer */
        App_cacheWb(appChObj->destBuf, APP_NUM_BYTES);

        /* Updated TRPD */
        App_trpdInit(appChObj, inst);

        /* Submit TRPD to channel */
        retVal = Udma_ringQueueRaw(
                     Udma_chGetFqRingHandle(chHandle),
                     (uint64_t) appChObj->trpd_mem_phy);
        if(UDMA_SOK != retVal)
        {
            App_print("[Error] Channel queue failed!!\n");
            break;
        }

    readback_index = 0;
    uint64_t *buf = (uint64_t *)appChObj->destBuf;    

    for(j=0;j<5;j++)
    {
            for (i = 0u; i < 30; i ++)
            {
                /* Now Trigger this GPIO */
                App_triggerGpio();
                appLogWaitMsecs(10);
            }

            App_setupL2G(appObj, 0);

            retVal = App_pause(appObj);
            if(UDMA_SOK != retVal)
            {
                App_print("[Error] UDMA App test Channel Disable Failed!!\n");
            }

            //  add readback to verify if  the package 
            index1=(j+1)*30 -15;    //
            index2=(j+1)*30 -3;

            App_cacheInv(appChObj->destBuf, APP_NUM_BYTES);
            test_readBackData[readback_index] = buf[ index1];
            test_readBackData[readback_index+1] =  buf[ index2];
            readback_index +=2;
            

            for (i = 0u; i < 30; i ++)
            {
                /* Now Trigger this GPIO */
                App_triggerGpio();
                appLogWaitMsecs(10);        
            }

            retVal = App_resume(appObj);
            if(UDMA_SOK != retVal)
            {
                App_print("[Error] UDMA App test Channel Enable Failed!!\n");
            }

            App_setupL2G(appObj, 1);
#if 0
            for (i = 0u; i < 20; i ++)
            {
                /* Now Trigger this GPIO */
                App_triggerGpio();
                appLogWaitMsecs(10);
            }
#endif            
    }        
#if 1

        App_cacheInv(appChObj->destBuf, APP_NUM_BYTES);

        {
            uint64_t *buf = (uint64_t *)appChObj->destBuf;
            for (i = 1u; i < APP_TIME_READ_CNT; i ++)
            {
				printf ("timer raw buf[%d] = %lld---buf[%d] = %lld\n", i, buf[i], (i-1), buf[i-1]);
                printf ("Diff %d\n", (uint32_t)(buf[i] - buf[i-1]));
            }
        }
#endif
    }

    return (retVal);
}

static void App_eventDmaCb(Udma_EventHandle eventHandle,
                               uint32_t eventType,
                               void *appData)
{
    App_ChObj *appChObj = (App_ChObj *) appData;

	printf ("Enter ----------- App_eventDmaCb()\n");
	
    if(appChObj != NULL)
    {
        if(UDMA_EVENT_TYPE_DMA_COMPLETION == eventType)
        {
            SemaphoreP_post(appChObj->transferDoneSem);
        }
        else
        {
            gUdmaAppResult = UDMA_EFAIL;
        }
    }
    else
    {
        gUdmaAppResult = UDMA_EFAIL;
    }

    return;
}

static void App_eventTdCb(Udma_EventHandle eventHandle,
                              uint32_t eventType,
                              void *appData)
{
    int32_t             retVal;
    CSL_UdmapTdResponse tdResp;
    App_ChObj      *appChObj = (App_ChObj *) appData;

	printf ("Enter ----------- App_eventTdCb()\n");
	
    if(appChObj != NULL)
    {
        if(UDMA_EVENT_TYPE_TEARDOWN_PACKET == eventType)
        {
            /* Response received in Teardown completion queue */
            retVal = Udma_chDequeueTdResponse(appChObj->chHandle, &tdResp);
            if(UDMA_SOK != retVal)
            {
                /* [Error] No TD response after callback!! */
                gUdmaAppResult = UDMA_EFAIL;
            }
        }
        else
        {
            gUdmaAppResult = UDMA_EFAIL;
        }
    }
    else
    {
        gUdmaAppResult = UDMA_EFAIL;
    }

    return;
}

static int32_t App_init(App_Obj *appObj)
{
    int32_t         retVal = UDMA_SOK;
    int32_t         chIdx;
    App_ChObj      *appChObj;
    Udma_DrvHandle  drvHandle;

    drvHandle = appObj->drvHandle = appUdmaGetObj();

    /* Init channel parameters */
    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        appChObj                    = &appObj->appChObj[chIdx];
        appChObj->chIdx             = chIdx;

        appChObj->chHandle          = &appChObj->chObj;
        appChObj->cqEventHandle     = NULL;
        appChObj->tdCqEventHandle   = NULL;
        appChObj->drvHandle         = drvHandle;
        appChObj->transferDoneSem   = NULL;
        appChObj->txRingMem         = appMemAlloc(APP_MEM_HEAP_DDR, APP_RING_MEM_SIZE_ALIGN, UDMA_CACHELINE_ALIGNMENT);
        appChObj->txCompRingMem     = appMemAlloc(APP_MEM_HEAP_DDR, APP_RING_MEM_SIZE_ALIGN, UDMA_CACHELINE_ALIGNMENT);
        appChObj->txTdCompRingMem   = appMemAlloc(APP_MEM_HEAP_DDR, APP_RING_MEM_SIZE_ALIGN, UDMA_CACHELINE_ALIGNMENT);
        appChObj->trpdMem           = appMemAlloc(APP_MEM_HEAP_DDR, APP_TRPD_SIZE_ALIGN, UDMA_CACHELINE_ALIGNMENT);

        //appChObj->destBuf = appMemAlloc(APP_MEM_HEAP_DDR_NON_CACHE, APP_BUF_SIZE_ALIGN*64, UDMA_CACHELINE_ALIGNMENT);
        appChObj->destBuf = appMemAlloc(APP_MEM_HEAP_DDR, APP_BUF_SIZE_ALIGN*128, UDMA_CACHELINE_ALIGNMENT);
        
        appChObj->trpd_mem_phy =
            appMemGetVirt2PhyBufPtr(
                (uint64_t) appChObj->trpdMem, APP_MEM_HEAP_DDR);
    }

    return (retVal);
}

static int32_t App_deinit(App_Obj *appObj)
{
    /* Release Driver Handle */
    appObj->drvHandle = NULL;

    return (UDMA_SOK);
}

static int32_t App_create(App_Obj *appObj)
{
    int32_t             retVal = UDMA_SOK;
    uint32_t            chType;
    Udma_ChPrms         chPrms;
    Udma_ChTxPrms       txPrms;
    Udma_ChRxPrms       rxPrms;
    Udma_EventHandle    eventHandle;
    Udma_EventPrms      eventPrms;
    SemaphoreP_Params   semPrms;
    int32_t             chIdx;
    App_ChObj          *appChObj;
    Udma_ChHandle       chHandle;
    Udma_DrvHandle      drvHandle = appObj->drvHandle;

    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        appChObj = &appObj->appChObj[chIdx];
        chHandle = appChObj->chHandle;

        SemaphoreP_Params_init(&semPrms);
        appChObj->transferDoneSem = SemaphoreP_create(0, &semPrms);
        if(NULL == appChObj->transferDoneSem)
        {
            App_print("[Error] Sem create failed!!\n");
            retVal = UDMA_EFAIL;
        }

        if(UDMA_SOK == retVal)
        {
            /* Init channel parameters */
            chType = UDMA_CH_TYPE_TR_BLK_COPY;
            UdmaChPrms_init(&chPrms, chType);
            chPrms.fqRingPrms.ringMem   = appChObj->txRingMem;
            chPrms.cqRingPrms.ringMem   = appChObj->txCompRingMem;
            chPrms.tdCqRingPrms.ringMem = appChObj->txTdCompRingMem;
            chPrms.fqRingPrms.ringMemSize   = APP_RING_MEM_SIZE;
            chPrms.cqRingPrms.ringMemSize   = APP_RING_MEM_SIZE;
            chPrms.tdCqRingPrms.ringMemSize = APP_RING_MEM_SIZE;

            chPrms.fqRingPrms.elemCnt   = APP_RING_ENTRIES;
            chPrms.cqRingPrms.elemCnt   = APP_RING_ENTRIES;
            chPrms.tdCqRingPrms.elemCnt = APP_RING_ENTRIES;

            /* Open channel for block copy */
            retVal = Udma_chOpen(drvHandle, chHandle, chType, &chPrms);
            if(UDMA_SOK != retVal)
            {
                App_print("[Error] UDMA channel open failed!!\n");
            }
			else
			{
				printf("chIdx:%d UDMA channel open sucess!\n" , chIdx);
			}
        }

        if(UDMA_SOK == retVal)
        {
            /* Config TX channel */
            UdmaChTxPrms_init(&txPrms, chType);
            retVal = Udma_chConfigTx(chHandle, &txPrms);
            if(UDMA_SOK != retVal)
            {
                App_print("[Error] UDMA TX channel config failed!!\n");
            }
			else
			{
				printf("chIdx:%d UDMA TX channel config sucess!\n" , chIdx);
			}
        }

        if(UDMA_SOK == retVal)
        {
            /* Config RX channel - which is implicitly paired to TX channel in
             * block copy mode */
            UdmaChRxPrms_init(&rxPrms, chType);
            retVal = Udma_chConfigRx(chHandle, &rxPrms);
            if(UDMA_SOK != retVal)
            {
                App_print("[Error] UDMA RX channel config failed!!\n");
            }
			else
			{
				printf("chIdx:%d UDMA RX channel config sucess!\n" , chIdx);
			}
        }

        if(UDMA_SOK == retVal)
        {
            /* Register ring completion callback - for the last channel only */
            eventHandle = &appChObj->cqEventObj;
            UdmaEventPrms_init(&eventPrms);
            eventPrms.eventType         = UDMA_EVENT_TYPE_DMA_COMPLETION;
            eventPrms.eventMode         = UDMA_EVENT_MODE_SHARED;
            eventPrms.chHandle          = chHandle;
            eventPrms.masterEventHandle = Udma_eventGetGlobalHandle(drvHandle);
            eventPrms.eventCb           = &App_eventDmaCb;
            eventPrms.appData           = appChObj;
            retVal = Udma_eventRegister(drvHandle, eventHandle, &eventPrms);
            if(UDMA_SOK != retVal)
            {
                App_print("[Error] UDMA CQ event register failed!!\n");
            }
            else
            {
                appChObj->cqEventHandle = eventHandle;
            }
        }

        if(UDMA_SOK == retVal)
        {
            /* Register teardown ring completion callback */
            eventHandle = &appChObj->tdCqEventObj;
            UdmaEventPrms_init(&eventPrms);
            eventPrms.eventType         = UDMA_EVENT_TYPE_TEARDOWN_PACKET;
            eventPrms.eventMode         = UDMA_EVENT_MODE_SHARED;
            eventPrms.chHandle          = chHandle;
            eventPrms.masterEventHandle = Udma_eventGetGlobalHandle(drvHandle);
            eventPrms.eventCb           = &App_eventTdCb;
            eventPrms.appData           = appChObj;
            retVal = Udma_eventRegister(drvHandle, eventHandle, &eventPrms);
            if(UDMA_SOK != retVal)
            {
                App_print("[Error] UDMA Teardown CQ event register failed!!\n");
            }
            else
            {
                appChObj->tdCqEventHandle = eventHandle;
            }
        }

        if(UDMA_SOK == retVal)
        {
            /* Channel enable */
            retVal = Udma_chEnable(chHandle);
            if(UDMA_SOK != retVal)
            {
                App_print("[Error] UDMA channel enable failed!!\n");
            }
        }

        if(UDMA_SOK != retVal)
        {
            break;
        }
    }

    /* Setup GPIO Pinmux */
    App_setupPinmux();

    /* Initialize GPIO now here */
    App_initGpio();

    /* Configure GPIO Mux to output event on Interrupt Aggregrator */
    App_setupGpioMuxIr();

    /* Setup L2G register to map local event to Global event */
    App_setupL2G(appObj, 1);

    return (retVal);
}

static int32_t App_resume(App_Obj *appObj)
{
    int32_t         retVal;
    int32_t         chIdx;
    App_ChObj  *appChObj;
    Udma_ChHandle   chHandle;

    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        appChObj = &appObj->appChObj[chIdx];
        chHandle = appChObj->chHandle;

        retVal = Udma_chResume(chHandle);
        if(UDMA_SOK != retVal)
        {
            App_print("[Error] UDMA channel disable failed!!\n");
        }
    }

    return 0;
}

static int32_t App_pause(App_Obj *appObj)
{
    int32_t         retVal;
    int32_t         chIdx;
    App_ChObj  *appChObj;
    Udma_ChHandle   chHandle;

    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        appChObj = &appObj->appChObj[chIdx];
        chHandle = appChObj->chHandle;

        retVal = Udma_chPause(chHandle);
        if(UDMA_SOK != retVal)
        {
            App_print("[Error] UDMA channel disable failed!!\n");
        }
    }

    return 0;
}

static int32_t App_delete(App_Obj *appObj)
{
    int32_t         retVal, tempRetVal;
    uint64_t        pDesc;
    int32_t         chIdx;
    App_ChObj  *appChObj;
    Udma_ChHandle   chHandle;

    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        appChObj = &appObj->appChObj[chIdx];
        chHandle = appChObj->chHandle;

        retVal = Udma_chDisable(chHandle, UDMA_DEFAULT_CH_DISABLE_TIMEOUT);
        if(UDMA_SOK != retVal)
        {
            App_print("[Error] UDMA channel disable failed!!\n");
        }

        /* Flush any pending request from the free queue */
        while(1)
        {
            tempRetVal = Udma_ringFlushRaw(
                             Udma_chGetFqRingHandle(chHandle), &pDesc);
            if(UDMA_ETIMEOUT == tempRetVal)
            {
                break;
            }
        }
    }

    for(chIdx = APP_NUM_CH - 1U; chIdx >=0 ; chIdx--)
    {
        appChObj = &appObj->appChObj[chIdx];
        chHandle = appChObj->chHandle;

        /* Unregister all events */
        if(NULL != appChObj->cqEventHandle)
        {
            retVal += Udma_eventUnRegister(appChObj->cqEventHandle);
            if(UDMA_SOK != retVal)
            {
                App_print("[Error] UDMA event unregister failed!!\n");
            }
            appChObj->cqEventHandle = NULL;
        }
        if(NULL != appChObj->tdCqEventHandle)
        {
            retVal += Udma_eventUnRegister(appChObj->tdCqEventHandle);
            if(UDMA_SOK != retVal)
            {
                App_print("[Error] UDMA event unregister failed!!\n");
            }
            appChObj->tdCqEventHandle = NULL;
        }

        retVal += Udma_chClose(chHandle);
        if(UDMA_SOK != retVal)
        {
            App_print("[Error] UDMA channel close failed!!\n");
        }

        if(appChObj->transferDoneSem != NULL)
        {
            SemaphoreP_delete(appChObj->transferDoneSem);
            appChObj->transferDoneSem = NULL;
        }
    }

    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        appChObj = &appObj->appChObj[chIdx];

        if (NULL != appChObj->txRingMem)
        {
            appMemFree(APP_MEM_HEAP_DDR, appChObj->txRingMem, UDMA_CACHELINE_ALIGNMENT);
            appChObj->txRingMem = NULL;
        }
        if (NULL != appChObj->txCompRingMem)
        {
            appMemFree(APP_MEM_HEAP_DDR, appChObj->txCompRingMem, UDMA_CACHELINE_ALIGNMENT);
            appChObj->txCompRingMem = NULL;
        }
        if (NULL != appChObj->txTdCompRingMem)
        {
            appMemFree(APP_MEM_HEAP_DDR, appChObj->txTdCompRingMem, UDMA_CACHELINE_ALIGNMENT);
            appChObj->txTdCompRingMem = NULL;
        }
        if (NULL != appChObj->trpdMem)
        {
            appMemFree(APP_MEM_HEAP_DDR, appChObj->trpdMem, UDMA_CACHELINE_ALIGNMENT);
            appChObj->trpdMem = NULL;
        }
        if (NULL != appChObj->destBuf)
        {
            appMemFree(APP_MEM_HEAP_DDR_NON_CACHE, appChObj->destBuf, UDMA_CACHELINE_ALIGNMENT);
            appChObj->destBuf = NULL;
        }
    }

    return (retVal);
}


static void App_trpdInit(App_ChObj *appChObj, uint32_t inst)
{
    CSL_UdmapCppi5TRPD *pTrpd = (CSL_UdmapCppi5TRPD *) appChObj->trpdMem;
    CSL_UdmapTR15 *pTr = (CSL_UdmapTR15 *)(appChObj->trpdMem + sizeof(CSL_UdmapTR15));
    uint32_t *pTrResp = (uint32_t *) (appChObj->trpdMem + (sizeof(CSL_UdmapTR15) * 2U));
    uint32_t cqRingNum = Udma_chGetCqRingNum(appChObj->chHandle);

    /* Make TRPD */
    UdmaUtils_makeTrpd(pTrpd, UDMA_TR_TYPE_15, 1U, cqRingNum);

    /* Reload indefinately */
    CSL_udmapCppi5TrSetReload((CSL_UdmapCppi5TRPD*)pTrpd, 0x1FF, 0U);

    /* Setup TR */
    pTr->flags  = CSL_FMK(UDMAP_TR_FLAGS_TYPE, CSL_UDMAP_TR_FLAGS_TYPE_4D_BLOCK_MOVE_REPACKING_INDIRECTION);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_STATIC, 0U);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EOL, 1U);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EVENT_SIZE, CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION);

    #if 1
    if (TRIGGER_TYPE == CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0)
    {
        pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0, CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0);
        pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0_TYPE, /*CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL*/ CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ICNT1_DEC);
    }
    else
    {
        pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0, CSL_UDMAP_TR_FLAGS_TRIGGER_NONE);
    }

    if (TRIGGER_TYPE == CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL1)
    {
        pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1, CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL1);
    }
    else
    {
        pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1, CSL_UDMAP_TR_FLAGS_TRIGGER_NONE);
    }
    #else

    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0, CSL_UDMAP_TR_FLAGS_TRIGGER_NONE);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1, CSL_UDMAP_TR_FLAGS_TRIGGER_NONE);
    #endif

    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1_TYPE, CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL);

    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_CMD_ID, 0x25U);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_SA_INDIRECT, 0U);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_DA_INDIRECT, 0U);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EOP, 1U);

    pTr->icnt0    = 8U;
    pTr->icnt1    = APP_TIME_READ_CNT;
    pTr->icnt2    = 1u;
    pTr->icnt3    = 1U;
    pTr->dim1     = 0;
    pTr->dim2     = 0;
    pTr->dim3     = 0;
    pTr->addr     = (uint64_t) (GTC_TIME_ADDR)/*appChObj->srcBuf*/;
    pTr->fmtflags = 0x00000000U;        /* Linear addressing, 1 byte per elem.
                                           Replace with CSL-FL API */
    pTr->dicnt0   = 8U;
    pTr->dicnt1   = APP_TIME_READ_CNT;
    pTr->dicnt2   = 1u;
    pTr->dicnt3   = 1U;
    pTr->ddim1    = pTr->dicnt0;
    pTr->ddim2    = 0;
    pTr->ddim3    = 0;
    pTr->daddr    = (uint64_t) appChObj->destBuf;

    /* Clear TR response memory */
    *pTrResp = 0xFFFFFFFFU;

    /* Writeback cache */
    App_cacheWb(appChObj->trpdMem, APP_TRPD_SIZE_ALIGN);

    return;
}

static uint32_t Udma_chGetTriggerEvent_2(Udma_DrvHandle drvHandle,
                                       Udma_ChHandle chHandle,
                                       uint32_t trigger)
{
    uint32_t        triggerEvent = UDMA_EVENT_INVALID;

    if((CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0 == trigger) ||
       (CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL1 == trigger))
    {
        /* Global 0/1 triggers are interleaved - so multiply by 2 */
        if(((chHandle->chType & UDMA_CH_FLAG_BLK_COPY) == UDMA_CH_FLAG_BLK_COPY) ||
           ((chHandle->chType & UDMA_CH_FLAG_TX) == UDMA_CH_FLAG_TX))
        {
            /* For block copy return the TX channel trigger */
            triggerEvent = (chHandle->txChNum * 2U);
            if(CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL1 == trigger)
            {
                triggerEvent++; /* Global1 trigger is next to global0 */
            }
            /* Add the global offset */
            triggerEvent += drvHandle->trigGemOffset;
        }
        else if((chHandle->chType & UDMA_CH_FLAG_RX) == UDMA_CH_FLAG_RX)
        {
#if 0
            /* RX trigger is after TX channel triggers
             * Note: There is no external channel triggers - hence not
             * using rxChOffset */
#if (UDMA_SOC_CFG_UDMAP_PRESENT == 1)
            if(UDMA_INST_TYPE_NORMAL == drvHandle->instType)
            {
                triggerEvent  = (drvHandle->udmapRegs.txChanCnt * 2U);
            }
#endif
#if (UDMA_SOC_CFG_LCDMA_PRESENT == 1)
            if(UDMA_INST_TYPE_LCDMA_BCDMA == drvHandle->instType)
            {
                triggerEvent  = (drvHandle->bcdmaRegs.txChanCnt * 2U);
            }
            else if(UDMA_INST_TYPE_LCDMA_PKTDMA == drvHandle->instType)
            {
                triggerEvent  = (drvHandle->pktdmaRegs.txChanCnt * 2U);
            }
#endif
#endif

            triggerEvent += (chHandle->rxChNum * 2U);
            if(CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL1 == trigger)
            {
                triggerEvent++; /* Global1 trigger is next to global0 */
            }
            /* Add the global offset */
            triggerEvent += drvHandle->trigGemOffset;
        }
        else
        {
            /* Trigger not supported for external channel -
             * return no event - already set */
        }
    }

    return (triggerEvent);
}

static void App_setupL2G(App_Obj *appObj, uint32_t enable)
{
    uint32_t                chIdx;
    uint32_t                triggerEvent;
    App_ChObj              *appChObj;
    Udma_ChHandle           chHandle;

    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        appChObj = &appObj->appChObj[chIdx];
        chHandle = appChObj->chHandle;

        triggerEvent =
                Udma_chGetTriggerEvent_2(appChObj->drvHandle,
                    chHandle, TRIGGER_TYPE);

        App_setUdmaIntAMap(appObj, gIntAggrLeviEvtId[chIdx + INTR_OFFSET], triggerEvent, enable);
    }
}

static void App_setUdmaIntAMap(App_Obj *appObj, uint32_t localEvtIdx, uint32_t glblEvt, uint32_t enable)
{
    uint32_t intaOffset = (CSL_NAVSS0_UDMASS_INTA0_CFG_L2G_BASE + (localEvtIdx) * 0x20u);

    if (enable)
    {
        /* Enable Rising Event */
        *((uint32_t *)intaOffset) = (1u << 31u) | (glblEvt & 0xFFFFu);
    }
    else
    {
        *((uint32_t *)intaOffset) = 0;
    }
}

#if 0
static void App_setupPinmux()
{
    /* Setup GPIO 37 */
    *(volatile uint32_t *)0x11c094 = 0x50007 | (2 << 4);
    *(volatile uint32_t *)0x11c098 = 0x50007 | (2 << 4);
    *(volatile uint32_t *)0x11c09C = 0x50007 | (2 << 4);
}

static void App_initGpio()
{
    uint32_t chIdx, bitpos, gpio_id, bank_id;

    for (chIdx = 0; chIdx < APP_NUM_CH; chIdx ++)
    {
        gpio_id = GPIO_START + chIdx;
        bitpos = gpio_id % 32;
        bank_id = gpio_id / 16;

        *(volatile uint32_t *)0x00620044 = (1u << bitpos);
        *(volatile uint32_t *)0x00620038 &= ~(1u << bitpos);

        *(volatile uint32_t *)0x0062004C = (1u << bitpos);
        *(volatile uint32_t *)0x00620054 = (1u << bitpos);

        *(volatile uint32_t *)0x0062005C = (1u << bitpos);

        *(volatile uint32_t *)0x00620044 = (1u << bitpos);
        *(volatile uint32_t *)0x00620038 &= ~(1u << bitpos);

        *(volatile uint32_t *)0x00620008 = (1u << bank_id);

        *(volatile uint32_t *)0x0062004C = (1u << bitpos);
        *(volatile uint32_t *)0x00620054 = (1u << bitpos);
    }
}

static void App_setupGpioMuxIr()
{
    int32_t                             status;
    uint32_t                            chIdx;
    struct tisci_msg_rm_irq_set_req     rmIrqReq;
    struct tisci_msg_rm_irq_set_resp    rmIrqResp;

    memset(&rmIrqReq, 0x0, sizeof(rmIrqReq));
    memset(&rmIrqResp, 0x0, sizeof(rmIrqResp));

    rmIrqReq.valid_params           = 0U;
    rmIrqReq.global_event           = 0U;
    rmIrqReq.src_id                 = 0U;
    rmIrqReq.src_index              = 0U;
    rmIrqReq.dst_id                 = 0U;
    rmIrqReq.dst_host_irq           = 0U;
    rmIrqReq.ia_id                  = 0U;
    rmIrqReq.vint                   = 0U;
    rmIrqReq.vint_status_bit_index  = 0U;
    rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        rmIrqReq.src_id         = TISCI_DEV_GPIOMUX_INTRTR0;
        rmIrqReq.src_index      = GPIO_START + chIdx;

        /* Set the destination based on the core */
        rmIrqReq.dst_id         = TISCI_DEV_GPIOMUX_INTRTR0;
        rmIrqReq.dst_host_irq   = GPIOMUX_INTRTR0_OUTP_START_R5FSS0 + chIdx;

        /* Set the destination interrupt */
        rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
        rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;

        status = Sciclient_rmIrqSetRaw(
                   (const struct tisci_msg_rm_irq_set_req *)&rmIrqReq,
                    &rmIrqResp,
                    SCICLIENT_SERVICE_WAIT_FOREVER);

        if(status == CSL_PASS)
        {
            App_print ("Worked fine \n");
        }
        else
        {
            App_print ("Failed \n");
        }
    }
}

static void App_triggerGpio()
{
    uint32_t    chIdx;
    uint32_t    gpio_id;
    uint32_t    bitpos;
    static uint32_t iterCnt = 0;

    for (chIdx = 0; chIdx < APP_NUM_CH; chIdx ++)
    {
        gpio_id = GPIO_START + chIdx;
        bitpos = gpio_id % 32;

        if (iterCnt % 2 == 0)
        {
            /* Now set the data for both the GPIO,
               Both interrupts would be called,
               but in second loop on GPIO38 isr would be called */
            *(volatile uint32_t *)0x00620040 = (1u << bitpos);
        }
        else
        {
            /* Now set the data for both the GPIO,
               Both interrupts would be called,
               but in second loop on GPIO38 isr would be called */
            *(volatile uint32_t *)0x00620044 = (1u << bitpos);
        }
    }

    iterCnt ++;
}

#else
static void App_setupPinmux()
{
	*(volatile unsigned int *)(0x0011C0A4) = 0x60007; //CAP_FRS	T23 	GPIO0_41
	*(volatile unsigned int *)(0x0011C08C) = 0x60007; //CAP_FLS	T25 	GPIO0_35
	*(volatile unsigned int *)(0x0011C0B8) = 0x60007; //CAP_RRS	AA24	GPIO0_46
	*(volatile unsigned int *)(0x0011C098) = 0x60007; //CAP_RLS	V25 	GPIO0_38

	*(volatile unsigned int *)(0x0011C084) = 0x60007; //CAP_FLC	AA28	GPIO0_33
	*(volatile unsigned int *)(0x0011C09C) = 0x60007; //CAP_FRM	T24 	GPIO0_39
	*(volatile unsigned int *)(0x0011C0A8) = 0x60007; //CAP_FRC	U24 	GPIO0_42
	*(volatile unsigned int *)(0x0011C090) = 0x60007; //CAP_FLM	W24 	GPIO0_36

	*(volatile unsigned int *)(0x0011C088) = 0x60007; //CAP_RLC	AD27	GPIO0_34
	*(volatile unsigned int *)(0x0011C0A0) = 0x60007; //CAP_RRM	AB25	GPIO0_40
	*(volatile unsigned int *)(0x0011C0AC) = 0x60007; //CAP_RRC	AC25	GPIO0_43
	*(volatile unsigned int *)(0x0011C094) = 0x60007; //CAP_RLM	AA25	GPIO0_37
}

void App_initGpio()
{
    uint32_t chIdx, bitpos, gpio_id, bank_id;
	uint32_t offset = 0;

    for (chIdx = 0; chIdx < APP_NUM_CH; chIdx ++)
    {
        //gpio_id = GPIO_START + chIdx;
        gpio_id = gpio_input[chIdx];
        bitpos = gpio_id % 32;
        bank_id = gpio_id / 16;

		offset = gpio_id/32 * 0x28;

        /*GPIO_BINTEN*/
        //*(volatile uint32_t *)0x00600008 = (1u << bank_id);
        *(volatile uint32_t *)0x00600008 |= (1u << bank_id);

		/*GPIO_DIR*/
        *(volatile uint32_t *)(0x00600010+offset) |= (1u << bitpos);
		/*GPIO_SET_RIS_TRIG*/
        *(volatile uint32_t *)(0x00600024+offset) |= (1u << bitpos);
		/*GPIO_SET_FAL_TRIG*/
        *(volatile uint32_t *)(0x0060002c+offset) |= (1u << bitpos);
		/*GPIO_INTSTAT*/
        *(volatile uint32_t *)(0x00600034+offset) |= (1u << bitpos);

		//printf("[1] 0x00600008 = 0x%X\n", (1u << bank_id));
		//printf("[2] reg[0x%X] = 0x%X\n", (0x00600010+offset), (1u << bitpos));
		//printf("[3] reg[0x%X] = 0x%X\n", (0x00600024+offset), (1u << bitpos));
		//printf("[4] reg[0x%X] = 0x%X\n", (0x0060002c+offset), (1u << bitpos));
		//printf("[5] reg[0x%X] = 0x%X\n", (0x00600034+offset), (1u << bitpos));
    }
}
static void App_setupGpioMuxIr()
{
    int32_t                             status;
    uint32_t                            chIdx;
    struct tisci_msg_rm_irq_set_req     rmIrqReq;
    struct tisci_msg_rm_irq_set_resp    rmIrqResp;
	//int32_t i;

    memset(&rmIrqReq, 0x0, sizeof(rmIrqReq));
    memset(&rmIrqResp, 0x0, sizeof(rmIrqResp));

    rmIrqReq.valid_params           = 0U;
    rmIrqReq.global_event           = 0U;
    rmIrqReq.src_id                 = 0U;
    rmIrqReq.src_index              = 0U;
    rmIrqReq.dst_id                 = 0U;
    rmIrqReq.dst_host_irq           = 0U;
    rmIrqReq.ia_id                  = 0U;
    rmIrqReq.vint                   = 0U;
    rmIrqReq.vint_status_bit_index  = 0U;
    rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        rmIrqReq.src_id         = TISCI_DEV_GPIOMUX_INTRTR0;
        //rmIrqReq.src_index      = GPIO_START + chIdx;
        rmIrqReq.src_index      = gpio_input[chIdx];

        /* Set the destination based on the core */
        rmIrqReq.dst_id         = TISCI_DEV_GPIOMUX_INTRTR0;
        rmIrqReq.dst_host_irq   = GPIOMUX_INTRTR0_OUTP_START_R5FSS0 + chIdx;
        //rmIrqReq.dst_host_irq   = 16 + chIdx;
        //rmIrqReq.dst_host_irq   = 16;

        /* Set the destination interrupt */
        rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
        rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;

		printf("dst_host_irq=%d \n", rmIrqReq.dst_host_irq);
		status = Sciclient_rmIrqSetRaw(
				(const struct tisci_msg_rm_irq_set_req *)&rmIrqReq,
				&rmIrqResp,
				SCICLIENT_SERVICE_WAIT_FOREVER);

		if(status == CSL_PASS)
		{
			App_print ("Sciclient_rmIrqSetRaw Worked fine \n");
		}
		else
		{
			printf("Sciclient_rmIrqSetRaw Failed :%d\n", status);
		}
    }
}

static void App_triggerGpio()
{
    uint32_t    chIdx;
    uint32_t    gpio_id;
    uint32_t    bitpos;
	uint32_t    offset = 0;
    static uint32_t iterCnt = 0;

    for (chIdx = 0; chIdx < APP_NUM_CH; chIdx ++)
    {
		//gpio_id = gpio_input[chIdx];
		gpio_id = gpio_output[chIdx];
        bitpos = gpio_id % 32;
		offset = gpio_id/32 * 0x28;
		
        if (iterCnt % 2 == 0)
        {
            /* Now set the data for both the GPIO,
               Both interrupts would be called,
               but in second loop on GPIO38 isr would be called */
            //*(volatile uint32_t *)0x00620040 = (1u << bitpos);
			*(volatile uint32_t *)(0x00600018+offset)  = (1u << bitpos);
        }
        else
        {
            /* Now set the data for both the GPIO,
               Both interrupts would be called,
               but in second loop on GPIO38 isr would be called */
            //*(volatile uint32_t *)0x00620044 = (1u << bitpos);
			*(volatile uint32_t *)(0x0060001C+offset) = (1u << bitpos);
        }
    }

    iterCnt ++;
	//printf("iterCnt = %d \n", iterCnt);
}
#endif

static void App_print(const char *str)
{
    printf("%s", str);

    return;
}


static void App_cacheWb(const void *addr, int32_t size)
{
    CacheP_wb(addr, size);

    return;
}

static void App_cacheInv(const void * addr, int32_t size)
{
    CacheP_Inv(addr, size);

    return;
}

volatile uint32_t gWait = 0;
int32_t appGpioInit(void)
{
    /*Board_initCfg                       boardCfg;

    boardCfg = BOARD_INIT_PINMUX_CONFIG |
        BOARD_INIT_MODULE_CLOCK |
        BOARD_INIT_UART_STDIO | BOARD_INIT_UNLOCK_MMR |
        BOARD_INIT_PLL_MCU | BOARD_INIT_MODULE_CLOCK_MCU;

    Board_init(boardCfg);


    SET_DEVICE_STATE_ON(TISCI_DEV_GPIO0);
    //SET_DEVICE_STATE_ON(TISCI_DEV_GPIO1);
    SET_DEVICE_STATE_ON(TISCI_DEV_GPIO2);
    //SET_DEVICE_STATE_ON(TISCI_DEV_GPIO3);
    SET_DEVICE_STATE_ON(TISCI_DEV_GPIO4);
    //SET_DEVICE_STATE_ON(TISCI_DEV_GPIO5);
    SET_DEVICE_STATE_ON(TISCI_DEV_GPIO6);
    //SET_DEVICE_STATE_ON(TISCI_DEV_GPIO7);*/

    while (gWait);

    App_GpioDmaTest();

    return 0;
}

Hi Vinter,

I dont see INTSTAT register getting set when GPIO is toggled, this could be reason why it is not working..

Regards,

Brijesh

Hi Vinter,

Finally i could get it working. Can you please try with this file?

/*
 *
 * Copyright (c) 2018 Texas Instruments Incorporated
 *
 * All rights reserved not granted herein.
 *
 * Limited License.
 *
 * Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
 * license under copyrights and patents it now or hereafter owns or controls to make,
 * have made, use, import, offer to sell and sell ("Utilize") this software subject to the
 * terms herein.  With respect to the foregoing patent license, such license is granted
 * solely to the extent that any such patent is necessary to Utilize the software alone.
 * The patent license shall not apply to any combinations which include this software,
 * other than combinations with devices manufactured by or for TI ("TI Devices").
 * No hardware patent is licensed hereunder.
 *
 * Redistributions must preserve existing copyright notices and reproduce this license
 * (including the above copyright notice and the disclaimer and (if applicable) source
 * code license limitations below) in the documentation and/or other materials provided
 * with the distribution
 *
 * Redistribution and use in binary form, without modification, are permitted provided
 * that the following conditions are met:
 *
 * *       No reverse engineering, decompilation, or disassembly of this software is
 * permitted with respect to any software provided in binary form.
 *
 * *       any redistribution and use are licensed by TI for use only with TI Devices.
 *
 * *       Nothing shall obligate TI to provide you with source code for the software
 * licensed and provided to you in object code.
 *
 * If software source code is provided to you, modification and redistribution of the
 * source code are permitted provided that the following conditions are met:
 *
 * *       any redistribution and use of the source code, including any resulting derivative
 * works, are licensed by TI for use only with TI Devices.
 *
 * *       any redistribution and use of any object code compiled from the source code
 * and any resulting derivative works, are licensed by TI for use only with TI Devices.
 *
 * Neither the name of Texas Instruments Incorporated nor the names of its suppliers
 *
 * may be used to endorse or promote products derived from this software without
 * specific prior written permission.
 *
 * DISCLAIMER.
 *
 * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS
 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
 * OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

#include <stdio.h>
#include <string.h>
//#include <xdc/runtime/Error.h>
//#include <ti/sysbios/BIOS.h>
//#include <ti/sysbios/knl/Task.h>

#include <ti/board/board.h>
#include <ti/drv/gpio/GPIO.h>
#include <ti/drv/gpio/soc/GPIO_soc.h>
#include <ti/drv/gpio/src/v0/GPIO_v0.h>
#include <ti/csl/soc/j721s2/src/cslr_soc_baseaddress.h>
#include <ti/csl/src/ip/gpio/V0/gpio.h>

#include <ti/csl/csl_intr_router.h> /* CSL for interrupt router */
#include <ti/osal/osal.h>
#include <ti/drv/sciclient/sciclient.h>
#include <ti/csl/soc/j721s2/src/cslr_main_ctrl_mmr.h>
#include <ti/csl/soc/j721s2/src/cslr_soc_baseaddress.h>

#include <utils/sciclient/include/app_sciclient_wrapper_api.h>

#include <utils/mem/include/app_mem.h>
#include <ti/drv/udma/udma.h>

#include <utils/udma/include/app_udma.h>

//#include <platform/j721s2/rtos/mcu2_1/ultrasonic/snr_gpio.h>

/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */

/* Test application stack size */
#define APP_TSK_STACK_MAIN              (16U * 1024U)

/*
 * Application test parameters
 */

#define APP_TIME_READ_CNT     (200U)

/** \brief Number of bytes to copy and buffer allocation */
#define APP_NUM_BYTES         (8U * APP_TIME_READ_CNT)
/** \brief This ensures every channel memory is aligned */
#define APP_BUF_SIZE_ALIGN    ((APP_NUM_BYTES + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
/** \brief Number of channels */
#define APP_NUM_CH            (1U)

/*
 * Ring parameters
 */
/** \brief Number of ring entries - we can prime this much memcpy operations */
#define APP_RING_ENTRIES      (3U)
/** \brief Size (in bytes) of each ring entry (Size of pointer - 64-bit) */
#define APP_RING_ENTRY_SIZE   (sizeof(uint64_t))
/** \brief Total ring memory */
#define APP_RING_MEM_SIZE     (APP_RING_ENTRIES * \
                                         APP_RING_ENTRY_SIZE)
/** \brief This ensures every channel memory is aligned */
#define APP_RING_MEM_SIZE_ALIGN ((APP_RING_MEM_SIZE + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))
/**
 *  \brief UDMA TR packet descriptor memory.
 *  This contains the CSL_UdmapCppi5TRPD + Padding to sizeof(CSL_UdmapTR15) +
 *  one Type_15 TR (CSL_UdmapTR15) + one TR response of 4 bytes.
 *  Since CSL_UdmapCppi5TRPD is less than CSL_UdmapTR15, size is just two times
 *  CSL_UdmapTR15 for alignment.
 */
#define APP_TRPD_SIZE         ((sizeof(CSL_UdmapTR15) * 2U) + 4U)
/** \brief This ensures every channel memory is aligned */
#define APP_TRPD_SIZE_ALIGN   ((APP_TRPD_SIZE + UDMA_CACHELINE_ALIGNMENT) & ~(UDMA_CACHELINE_ALIGNMENT - 1U))


#define TRIGGER_TYPE          (CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0)

//uint32_t INTR_OFFSET = 8u;
uint32_t INTR_OFFSET = 0u;

//#define GPIOMUX_INTRTR0_OUTP_START_R5FSS0 (16u + INTR_OFFSET)
#define GPIOMUX_INTRTR0_OUTP_START_R5FSS0 (16 + INTR_OFFSET)

#define GPIO_START            (37)

#define GTC_TIME_ADDR         (0xA90008u)
volatile unsigned long long test_readBackData[50] = {0};

#define FRS_I 41//T23 GPIO0_41
#define FLS_I 35//T25 GPIO0_35
#define RRS_I 46//AA24 GPIO0_46
#define RLS_I 38//V25 GPIO0_38

#define FLC_I 33//AA28 GPIO0_33
#define FRM_I 39//T24 GPIO0_39
#define FRC_I 42//U24 GPIO0_42
#define FLM_I 36//W24 GPIO0_36

#define RLC_I 34//AD27 GPIO0_34
#define RRM_I 40//AB25 GPIO0_40
#define RRC_I 43//AC25 GPIO0_43
#define RLM_I 37//AA25 GPIO0_37

uint8_t gpio_input[APP_NUM_CH] = {
    FLC_I,  FRM_I, FLM_I, FRC_I,
    RLC_I,  RRM_I, RLM_I, RRC_I,
    FRS_I,  RRS_I, FLS_I, RLS_I,
};

#if 0
uint32_t gpio_output[] = {
    FLC_O, FLM_O, FRM_O, FRC_O,
    RLC_O, RLM_O, RRM_O, RRC_O,
    FRS_O, RRS_O, FLS_O, RLS_O,
};
#endif

/* ========================================================================== */
/*                         Structure Declarations                             */
/* ========================================================================== */

typedef struct
{
    int32_t                 chIdx;

    struct Udma_ChObj       chObj;
    struct Udma_EventObj    cqEventObj;
    struct Udma_EventObj    tdCqEventObj;

    Udma_ChHandle           chHandle;
    Udma_EventHandle        cqEventHandle;
    Udma_EventHandle        tdCqEventHandle;

    Udma_DrvHandle          drvHandle;
    SemaphoreP_Handle       transferDoneSem;
    /**< Semaphore to indicate transfer completion */

    uint8_t                 *txRingMem;
    uint8_t                 *txCompRingMem;
    uint8_t                 *txTdCompRingMem;
    uint8_t                 *trpdMem;

    uint64_t                trpd_mem_phy;
    /**< Allocated TRPD memory physical pointer */

    uint8_t                 *destBuf;
} App_ChObj;

typedef struct
{
    Udma_DrvHandle          drvHandle;
    App_ChObj               appChObj[APP_NUM_CH];
} App_Obj;

/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */

static int32_t App_GpioDmaTest(void);

static int32_t App_gpioTriggerTest(App_Obj *appObj, uint32_t inst);

static void App_eventDmaCb(Udma_EventHandle eventHandle,
                           uint32_t eventType,
                           void *appData);
static void App_eventTdCb(Udma_EventHandle eventHandle,
                          uint32_t eventType,
                          void *appData);

static int32_t App_init(App_Obj *appObj);
static int32_t App_deinit(App_Obj *appObj);

static int32_t App_create(App_Obj *appObj);
static int32_t App_delete(App_Obj *appObj);

static void App_trpdInit(App_ChObj *appChObj, uint32_t inst);

static void App_print(const char *str);

static void App_setupPinmux();
//static uint32_t Udma_chGetTriggerEvent_2(Udma_DrvHandle drvHandle,
//                                       Udma_ChHandle chHandle,
//                                       uint32_t trigger);
static void App_setupL2G(App_Obj *appObj, uint32_t enable);
static void App_setUdmaIntAMap(App_Obj *appObj, uint32_t localEvtIdx, uint32_t glblEvt, uint32_t enable);
static void App_initGpio();
static void App_setupGpioMuxIr();
static void App_triggerGpio();

static void App_cacheInv(const void * addr, int32_t size);
static void App_cacheWb(const void *addr, int32_t size);

static int32_t App_pause(App_Obj *appObj);
static int32_t App_resume(App_Obj *appObj);

/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */

/*
 * UDMA driver and channel objects
 */
App_Obj gAppObj;

#if 0
/*
 * UDMA Memories
 */
static uint8_t gTxRingMem[APP_NUM_CH][APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
static uint8_t gTxCompRingMem[APP_NUM_CH][APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
static uint8_t gTxTdCompRingMem[APP_NUM_CH][APP_RING_MEM_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
static uint8_t gUdmaTrpdMem[APP_NUM_CH][APP_TRPD_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
#endif

#if 0
/*
 * Application Buffers
 */
static uint8_t gUdmaTestSrcBuf[APP_NUM_CH][APP_BUF_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
static uint8_t gUdmaTestDestBuf[APP_NUM_CH][APP_BUF_SIZE_ALIGN] __attribute__((aligned(UDMA_CACHELINE_ALIGNMENT)));
#endif

/* Global test pass/fail flag */
static volatile int32_t gUdmaAppResult = UDMA_SOK;

static volatile uint32_t gIntAggrLeviEvtId[16] = {
        116, 117, 118, 119, 120, 121, 122, 123,
        124, 125, 126, 127, 128, 129, 130, 131};

/* Test application stack */
//static uint8_t  gAppTskStackMain[APP_TSK_STACK_MAIN] __attribute__((aligned(32)));;

/* ========================================================================== */
/*                          Function Definitions                              */
/* ========================================================================== */

static int32_t App_GpioDmaTest(void)
{
    int32_t     retVal;
    App_Obj    *appObj = &gAppObj;

    retVal = App_init(appObj);
    if(UDMA_SOK != retVal)
    {
        App_print("[Error] UDMA App init failed!!\n");
    }

    App_print("Application started...\n");

    if(UDMA_SOK == retVal)
    {
        retVal = App_create(appObj);
        if(UDMA_SOK != retVal)
        {
            App_print("[Error] UDMA App create failed!!\n");
        }
    }

    if(UDMA_SOK == retVal)
    {
        retVal = App_gpioTriggerTest(appObj, 0);
        if(UDMA_SOK != retVal)
        {
            App_print("[Error] UDMA App test failed!!\n");
        }
    }

    retVal += App_delete(appObj);
    if(UDMA_SOK != retVal)
    {
        App_print("[Error] UDMA App delete failed!!\n");
    }

    retVal += App_deinit(appObj);
    if(UDMA_SOK != retVal)
    {
        App_print("[Error] UDMA App deinit failed!!\n");
    }

    if((UDMA_SOK == retVal) && (UDMA_SOK == gUdmaAppResult))
    {
        App_print("Passed!!\n");
        App_print("All tests have passed!!\n");
    }
    else
    {
        App_print("Failed!!\n");
        App_print("Some tests have failed!!\n");
    }

    if(UDMA_SOK == gUdmaAppResult)
         App_print("gUdmaAppResult == UDMA_SOK!!\n");
    else
        App_print("gUdmaAppResult == UDMA_EFAIL!!\n");

    return (0);
}

static int32_t App_gpioTriggerTest(App_Obj *appObj, uint32_t inst)
{
    int32_t         retVal = UDMA_SOK;
    int32_t         chIdx;
    App_ChObj      *appChObj;
    uint32_t        i,j;
    uint8_t        *destBuf;
    Udma_ChHandle   chHandle;
    //uint64_t        pDesc = 0;
    //uint32_t       *pTrResp, trRespStatus;

    /* Reset dest buffers */
    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        appChObj = &appObj->appChObj[chIdx];
        chHandle = appChObj->chHandle;
        destBuf  = appChObj->destBuf;

        for(i = 0U; i < APP_NUM_BYTES; i++)
        {
            destBuf[i] = 0U;
        }
        /* Writeback destination buffer */
        App_cacheWb(appChObj->destBuf, APP_NUM_BYTES);

        /* Updated TRPD */
        App_trpdInit(appChObj, inst);

        /* Submit TRPD to channel */
        retVal = Udma_ringQueueRaw(
                     Udma_chGetFqRingHandle(chHandle),
                     (uint64_t) appChObj->trpd_mem_phy);
        if(UDMA_SOK != retVal)
        {
            App_print("[Error] Channel queue failed!!\n");
            break;
        }

        for (i = 0u; i < APP_TIME_READ_CNT; i ++)
        {
            /* Now Trigger this GPIO */
            App_triggerGpio();
            appLogWaitMsecs(10);
        }

        SemaphoreP_pend(appChObj->transferDoneSem, SemaphoreP_WAIT_FOREVER);
#if 1

        App_cacheInv(appChObj->destBuf, APP_NUM_BYTES);

        {
            uint64_t *buf = (uint64_t *)appChObj->destBuf;
            for (i = 1u; i < APP_TIME_READ_CNT; i ++)
            {
                printf ("timer raw buf[%d] = %lld---buf[%d] = %lld\n", i, buf[i], (i-1), buf[i-1]);
                printf ("Diff %d\n", (uint32_t)(buf[i] - buf[i-1]));
            }
        }
#endif
    }

    return (retVal);
}

static void App_eventDmaCb(Udma_EventHandle eventHandle,
                               uint32_t eventType,
                               void *appData)
{
    App_ChObj *appChObj = (App_ChObj *) appData;

    printf ("Enter ----------- App_eventDmaCb()\n");

    if(appChObj != NULL)
    {
        if(UDMA_EVENT_TYPE_DMA_COMPLETION == eventType)
        {
            SemaphoreP_post(appChObj->transferDoneSem);
        }
        else
        {
            gUdmaAppResult = UDMA_EFAIL;
        }
    }
    else
    {
        gUdmaAppResult = UDMA_EFAIL;
    }

    return;
}

static void App_eventTdCb(Udma_EventHandle eventHandle,
                              uint32_t eventType,
                              void *appData)
{
    int32_t             retVal;
    CSL_UdmapTdResponse tdResp;
    App_ChObj      *appChObj = (App_ChObj *) appData;

    printf ("Enter ----------- App_eventTdCb()\n");

    if(appChObj != NULL)
    {
        if(UDMA_EVENT_TYPE_TEARDOWN_PACKET == eventType)
        {
            /* Response received in Teardown completion queue */
            retVal = Udma_chDequeueTdResponse(appChObj->chHandle, &tdResp);
            if(UDMA_SOK != retVal)
            {
                /* [Error] No TD response after callback!! */
                gUdmaAppResult = UDMA_EFAIL;
            }
        }
        else
        {
            gUdmaAppResult = UDMA_EFAIL;
        }
    }
    else
    {
        gUdmaAppResult = UDMA_EFAIL;
    }

    return;
}

static int32_t App_init(App_Obj *appObj)
{
    int32_t         retVal = UDMA_SOK;
    int32_t         chIdx;
    App_ChObj      *appChObj;
    Udma_DrvHandle  drvHandle;

    drvHandle = appObj->drvHandle = appUdmaGetObj();

    /* Init channel parameters */
    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        appChObj                    = &appObj->appChObj[chIdx];
        appChObj->chIdx             = chIdx;

        appChObj->chHandle          = &appChObj->chObj;
        appChObj->cqEventHandle     = NULL;
        appChObj->tdCqEventHandle   = NULL;
        appChObj->drvHandle         = drvHandle;
        appChObj->transferDoneSem   = NULL;
        appChObj->txRingMem         = appMemAlloc(APP_MEM_HEAP_DDR, APP_RING_MEM_SIZE_ALIGN, UDMA_CACHELINE_ALIGNMENT);
        appChObj->txCompRingMem     = appMemAlloc(APP_MEM_HEAP_DDR, APP_RING_MEM_SIZE_ALIGN, UDMA_CACHELINE_ALIGNMENT);
        appChObj->txTdCompRingMem   = appMemAlloc(APP_MEM_HEAP_DDR, APP_RING_MEM_SIZE_ALIGN, UDMA_CACHELINE_ALIGNMENT);
        appChObj->trpdMem           = appMemAlloc(APP_MEM_HEAP_DDR, APP_TRPD_SIZE_ALIGN, UDMA_CACHELINE_ALIGNMENT);

        //appChObj->destBuf = appMemAlloc(APP_MEM_HEAP_DDR_NON_CACHE, APP_BUF_SIZE_ALIGN*64, UDMA_CACHELINE_ALIGNMENT);
        appChObj->destBuf = appMemAlloc(APP_MEM_HEAP_DDR, APP_BUF_SIZE_ALIGN*128, UDMA_CACHELINE_ALIGNMENT);

        appChObj->trpd_mem_phy =
            appMemGetVirt2PhyBufPtr(
                (uint64_t) appChObj->trpdMem, APP_MEM_HEAP_DDR);
    }

    return (retVal);
}

static int32_t App_deinit(App_Obj *appObj)
{
    /* Release Driver Handle */
    appObj->drvHandle = NULL;

    return (UDMA_SOK);
}

static int32_t App_create(App_Obj *appObj)
{
    int32_t             retVal = UDMA_SOK;
    uint32_t            chType;
    Udma_ChPrms         chPrms;
    Udma_ChTxPrms       txPrms;
    Udma_ChRxPrms       rxPrms;
    Udma_EventHandle    eventHandle;
    Udma_EventPrms      eventPrms;
    SemaphoreP_Params   semPrms;
    int32_t             chIdx;
    App_ChObj          *appChObj;
    Udma_ChHandle       chHandle;
    Udma_DrvHandle      drvHandle = appObj->drvHandle;

    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        appChObj = &appObj->appChObj[chIdx];
        chHandle = appChObj->chHandle;

        SemaphoreP_Params_init(&semPrms);
        appChObj->transferDoneSem = SemaphoreP_create(0, &semPrms);
        if(NULL == appChObj->transferDoneSem)
        {
            App_print("[Error] Sem create failed!!\n");
            retVal = UDMA_EFAIL;
        }

        if(UDMA_SOK == retVal)
        {
            /* Init channel parameters */
            chType = UDMA_CH_TYPE_TR_BLK_COPY;
            UdmaChPrms_init(&chPrms, chType);
            chPrms.fqRingPrms.ringMem   = appChObj->txRingMem;
            chPrms.cqRingPrms.ringMem   = appChObj->txCompRingMem;
            chPrms.tdCqRingPrms.ringMem = appChObj->txTdCompRingMem;
            chPrms.fqRingPrms.ringMemSize   = APP_RING_MEM_SIZE;
            chPrms.cqRingPrms.ringMemSize   = APP_RING_MEM_SIZE;
            chPrms.tdCqRingPrms.ringMemSize = APP_RING_MEM_SIZE;

            chPrms.fqRingPrms.elemCnt   = APP_RING_ENTRIES;
            chPrms.cqRingPrms.elemCnt   = APP_RING_ENTRIES;
            chPrms.tdCqRingPrms.elemCnt = APP_RING_ENTRIES;

            /* Open channel for block copy */
            retVal = Udma_chOpen(drvHandle, chHandle, chType, &chPrms);
            if(UDMA_SOK != retVal)
            {
                App_print("[Error] UDMA channel open failed!!\n");
            }
            else
            {
                printf("chIdx:%d UDMA channel open sucess!\n" , chIdx);
            }
        }

        if(UDMA_SOK == retVal)
        {
            /* Config TX channel */
            UdmaChTxPrms_init(&txPrms, chType);
            retVal = Udma_chConfigTx(chHandle, &txPrms);
            if(UDMA_SOK != retVal)
            {
                App_print("[Error] UDMA TX channel config failed!!\n");
            }
            else
            {
                printf("chIdx:%d UDMA TX channel config sucess!\n" , chIdx);
            }
        }

        if(UDMA_SOK == retVal)
        {
            /* Config RX channel - which is implicitly paired to TX channel in
             * block copy mode */
            UdmaChRxPrms_init(&rxPrms, chType);
            retVal = Udma_chConfigRx(chHandle, &rxPrms);
            if(UDMA_SOK != retVal)
            {
                App_print("[Error] UDMA RX channel config failed!!\n");
            }
            else
            {
                printf("chIdx:%d UDMA RX channel config sucess!\n" , chIdx);
            }
        }

        if(UDMA_SOK == retVal)
        {
            /* Register ring completion callback - for the last channel only */
            eventHandle = &appChObj->cqEventObj;
            UdmaEventPrms_init(&eventPrms);
            eventPrms.eventType         = UDMA_EVENT_TYPE_DMA_COMPLETION;
            eventPrms.eventMode         = UDMA_EVENT_MODE_SHARED;
            eventPrms.chHandle          = chHandle;
            eventPrms.masterEventHandle = Udma_eventGetGlobalHandle(drvHandle);
            eventPrms.eventCb           = &App_eventDmaCb;
            eventPrms.appData           = appChObj;
            retVal = Udma_eventRegister(drvHandle, eventHandle, &eventPrms);
            if(UDMA_SOK != retVal)
            {
                App_print("[Error] UDMA CQ event register failed!!\n");
            }
            else
            {
                appChObj->cqEventHandle = eventHandle;
            }
        }

        if(UDMA_SOK == retVal)
        {
            /* Register teardown ring completion callback */
            eventHandle = &appChObj->tdCqEventObj;
            UdmaEventPrms_init(&eventPrms);
            eventPrms.eventType         = UDMA_EVENT_TYPE_TEARDOWN_PACKET;
            eventPrms.eventMode         = UDMA_EVENT_MODE_SHARED;
            eventPrms.chHandle          = chHandle;
            eventPrms.masterEventHandle = Udma_eventGetGlobalHandle(drvHandle);
            eventPrms.eventCb           = &App_eventTdCb;
            eventPrms.appData           = appChObj;
            retVal = Udma_eventRegister(drvHandle, eventHandle, &eventPrms);
            if(UDMA_SOK != retVal)
            {
                App_print("[Error] UDMA Teardown CQ event register failed!!\n");
            }
            else
            {
                appChObj->tdCqEventHandle = eventHandle;
            }
        }

        if(UDMA_SOK == retVal)
        {
            /* Channel enable */
            retVal = Udma_chEnable(chHandle);
            if(UDMA_SOK != retVal)
            {
                App_print("[Error] UDMA channel enable failed!!\n");
            }
        }

        if(UDMA_SOK != retVal)
        {
            break;
        }
    }

    /* Setup GPIO Pinmux */
    App_setupPinmux();

    /* Initialize GPIO now here */
    App_initGpio();

    /* Configure GPIO Mux to output event on Interrupt Aggregrator */
    App_setupGpioMuxIr();

    /* Setup L2G register to map local event to Global event */
    App_setupL2G(appObj, 1);

    return (retVal);
}

static int32_t App_resume(App_Obj *appObj)
{
    int32_t         retVal;
    int32_t         chIdx;
    App_ChObj  *appChObj;
    Udma_ChHandle   chHandle;

    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        appChObj = &appObj->appChObj[chIdx];
        chHandle = appChObj->chHandle;

        retVal = Udma_chResume(chHandle);
        if(UDMA_SOK != retVal)
        {
            App_print("[Error] UDMA channel disable failed!!\n");
        }
    }

    return 0;
}

static int32_t App_pause(App_Obj *appObj)
{
    int32_t         retVal;
    int32_t         chIdx;
    App_ChObj  *appChObj;
    Udma_ChHandle   chHandle;

    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        appChObj = &appObj->appChObj[chIdx];
        chHandle = appChObj->chHandle;

        retVal = Udma_chPause(chHandle);
        if(UDMA_SOK != retVal)
        {
            App_print("[Error] UDMA channel disable failed!!\n");
        }
    }

    return 0;
}

static int32_t App_delete(App_Obj *appObj)
{
    int32_t         retVal, tempRetVal;
    uint64_t        pDesc;
    int32_t         chIdx;
    App_ChObj  *appChObj;
    Udma_ChHandle   chHandle;

    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        appChObj = &appObj->appChObj[chIdx];
        chHandle = appChObj->chHandle;

        retVal = Udma_chDisable(chHandle, UDMA_DEFAULT_CH_DISABLE_TIMEOUT);
        if(UDMA_SOK != retVal)
        {
            App_print("[Error] UDMA channel disable failed!!\n");
        }

        /* Flush any pending request from the free queue */
        while(1)
        {
            tempRetVal = Udma_ringFlushRaw(
                             Udma_chGetFqRingHandle(chHandle), &pDesc);
            if(UDMA_ETIMEOUT == tempRetVal)
            {
                break;
            }
        }
    }

    for(chIdx = APP_NUM_CH - 1U; chIdx >=0 ; chIdx--)
    {
        appChObj = &appObj->appChObj[chIdx];
        chHandle = appChObj->chHandle;

        /* Unregister all events */
        if(NULL != appChObj->cqEventHandle)
        {
            retVal += Udma_eventUnRegister(appChObj->cqEventHandle);
            if(UDMA_SOK != retVal)
            {
                App_print("[Error] UDMA event unregister failed!!\n");
            }
            appChObj->cqEventHandle = NULL;
        }
        if(NULL != appChObj->tdCqEventHandle)
        {
            retVal += Udma_eventUnRegister(appChObj->tdCqEventHandle);
            if(UDMA_SOK != retVal)
            {
                App_print("[Error] UDMA event unregister failed!!\n");
            }
            appChObj->tdCqEventHandle = NULL;
        }

        retVal += Udma_chClose(chHandle);
        if(UDMA_SOK != retVal)
        {
            App_print("[Error] UDMA channel close failed!!\n");
        }

        if(appChObj->transferDoneSem != NULL)
        {
            SemaphoreP_delete(appChObj->transferDoneSem);
            appChObj->transferDoneSem = NULL;
        }
    }

    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        appChObj = &appObj->appChObj[chIdx];

        if (NULL != appChObj->txRingMem)
        {
            appMemFree(APP_MEM_HEAP_DDR, appChObj->txRingMem, UDMA_CACHELINE_ALIGNMENT);
            appChObj->txRingMem = NULL;
        }
        if (NULL != appChObj->txCompRingMem)
        {
            appMemFree(APP_MEM_HEAP_DDR, appChObj->txCompRingMem, UDMA_CACHELINE_ALIGNMENT);
            appChObj->txCompRingMem = NULL;
        }
        if (NULL != appChObj->txTdCompRingMem)
        {
            appMemFree(APP_MEM_HEAP_DDR, appChObj->txTdCompRingMem, UDMA_CACHELINE_ALIGNMENT);
            appChObj->txTdCompRingMem = NULL;
        }
        if (NULL != appChObj->trpdMem)
        {
            appMemFree(APP_MEM_HEAP_DDR, appChObj->trpdMem, UDMA_CACHELINE_ALIGNMENT);
            appChObj->trpdMem = NULL;
        }
        if (NULL != appChObj->destBuf)
        {
            appMemFree(APP_MEM_HEAP_DDR_NON_CACHE, appChObj->destBuf, UDMA_CACHELINE_ALIGNMENT);
            appChObj->destBuf = NULL;
        }
    }

    return (retVal);
}


static void App_trpdInit(App_ChObj *appChObj, uint32_t inst)
{
    CSL_UdmapCppi5TRPD *pTrpd = (CSL_UdmapCppi5TRPD *) appChObj->trpdMem;
    CSL_UdmapTR15 *pTr = (CSL_UdmapTR15 *)(appChObj->trpdMem + sizeof(CSL_UdmapTR15));
    uint32_t *pTrResp = (uint32_t *) (appChObj->trpdMem + (sizeof(CSL_UdmapTR15) * 2U));
    uint32_t cqRingNum = Udma_chGetCqRingNum(appChObj->chHandle);

    /* Make TRPD */
    UdmaUtils_makeTrpd(pTrpd, UDMA_TR_TYPE_15, 1U, cqRingNum);

    /* Reload indefinately */
    //CSL_udmapCppi5TrSetReload((CSL_UdmapCppi5TRPD*)pTrpd, 0x1FF, 0U);

    /* Setup TR */
    pTr->flags  = CSL_FMK(UDMAP_TR_FLAGS_TYPE, CSL_UDMAP_TR_FLAGS_TYPE_4D_BLOCK_MOVE_REPACKING_INDIRECTION);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_STATIC, 0U);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EOL, 1U);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EVENT_SIZE, CSL_UDMAP_TR_FLAGS_EVENT_SIZE_COMPLETION);

    #if 1
    if (TRIGGER_TYPE == CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0)
    {
        pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0, CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0);
        pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0_TYPE, /*CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL*/ CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ICNT1_DEC);
    }
    else
    {
        pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0, CSL_UDMAP_TR_FLAGS_TRIGGER_NONE);
    }

    if (TRIGGER_TYPE == CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL1)
    {
        pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1, CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL1);
    }
    else
    {
        pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1, CSL_UDMAP_TR_FLAGS_TRIGGER_NONE);
    }
    #else

    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER0, CSL_UDMAP_TR_FLAGS_TRIGGER_NONE);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1, CSL_UDMAP_TR_FLAGS_TRIGGER_NONE);
    #endif

    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_TRIGGER1_TYPE, CSL_UDMAP_TR_FLAGS_TRIGGER_TYPE_ALL);

    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_CMD_ID, 0x25U);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_SA_INDIRECT, 0U);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_DA_INDIRECT, 0U);
    pTr->flags |= CSL_FMK(UDMAP_TR_FLAGS_EOP, 1U);

    pTr->icnt0    = 8U;
    pTr->icnt1    = APP_TIME_READ_CNT;
    pTr->icnt2    = 1u;
    pTr->icnt3    = 1U;
    pTr->dim1     = 0;
    pTr->dim2     = 0;
    pTr->dim3     = 0;
    pTr->addr     = (uint64_t) (GTC_TIME_ADDR)/*appChObj->srcBuf*/;
    pTr->fmtflags = 0x00000000U;        /* Linear addressing, 1 byte per elem.
                                           Replace with CSL-FL API */
    pTr->dicnt0   = 8U;
    pTr->dicnt1   = APP_TIME_READ_CNT;
    pTr->dicnt2   = 1u;
    pTr->dicnt3   = 1U;
    pTr->ddim1    = pTr->dicnt0;
    pTr->ddim2    = 0;
    pTr->ddim3    = 0;
    pTr->daddr    = (uint64_t) appChObj->destBuf;

    /* Clear TR response memory */
    *pTrResp = 0xFFFFFFFFU;

    /* Writeback cache */
    App_cacheWb(appChObj->trpdMem, APP_TRPD_SIZE_ALIGN);

    return;
}

#if 0
static uint32_t Udma_chGetTriggerEvent_2(Udma_DrvHandle drvHandle,
                                       Udma_ChHandle chHandle,
                                       uint32_t trigger)
{
    uint32_t        triggerEvent = UDMA_EVENT_INVALID;

    if((CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL0 == trigger) ||
       (CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL1 == trigger))
    {
        /* Global 0/1 triggers are interleaved - so multiply by 2 */
        if(((chHandle->chType & UDMA_CH_FLAG_BLK_COPY) == UDMA_CH_FLAG_BLK_COPY) ||
           ((chHandle->chType & UDMA_CH_FLAG_TX) == UDMA_CH_FLAG_TX))
        {
            /* For block copy return the TX channel trigger */
            triggerEvent = (chHandle->txChNum * 2U);
            if(CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL1 == trigger)
            {
                triggerEvent++; /* Global1 trigger is next to global0 */
            }
            /* Add the global offset */
            triggerEvent += drvHandle->trigGemOffset;
        }
        else if((chHandle->chType & UDMA_CH_FLAG_RX) == UDMA_CH_FLAG_RX)
        {
#if 0
            /* RX trigger is after TX channel triggers
             * Note: There is no external channel triggers - hence not
             * using rxChOffset */
#if (UDMA_SOC_CFG_UDMAP_PRESENT == 1)
            if(UDMA_INST_TYPE_NORMAL == drvHandle->instType)
            {
                triggerEvent  = (drvHandle->udmapRegs.txChanCnt * 2U);
            }
#endif
#if (UDMA_SOC_CFG_LCDMA_PRESENT == 1)
            if(UDMA_INST_TYPE_LCDMA_BCDMA == drvHandle->instType)
            {
                triggerEvent  = (drvHandle->bcdmaRegs.txChanCnt * 2U);
            }
            else if(UDMA_INST_TYPE_LCDMA_PKTDMA == drvHandle->instType)
            {
                triggerEvent  = (drvHandle->pktdmaRegs.txChanCnt * 2U);
            }
#endif
#endif

            triggerEvent += (chHandle->rxChNum * 2U);
            if(CSL_UDMAP_TR_FLAGS_TRIGGER_GLOBAL1 == trigger)
            {
                triggerEvent++; /* Global1 trigger is next to global0 */
            }
            /* Add the global offset */
            triggerEvent += drvHandle->trigGemOffset;
        }
        else
        {
            /* Trigger not supported for external channel -
             * return no event - already set */
        }
    }

    return (triggerEvent);
}
#endif

static void App_setupL2G(App_Obj *appObj, uint32_t enable)
{
    uint32_t                chIdx;
    uint32_t                triggerEvent;
    App_ChObj              *appChObj;
    Udma_ChHandle           chHandle;

    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        appChObj = &appObj->appChObj[chIdx];
        chHandle = appChObj->chHandle;

        triggerEvent =
                Udma_chGetTriggerEvent(/*appChObj->drvHandle,*/
                    chHandle, TRIGGER_TYPE);

        App_setUdmaIntAMap(appObj, gIntAggrLeviEvtId[chIdx + INTR_OFFSET], triggerEvent, enable);
    }
}

static void App_setUdmaIntAMap(App_Obj *appObj, uint32_t localEvtIdx, uint32_t glblEvt, uint32_t enable)
{
    uint32_t intaOffset = (CSL_NAVSS0_UDMASS_INTA0_CFG_L2G_BASE + (localEvtIdx) * 0x20u);

    if (enable)
    {
        /* Enable Rising Event */
        *((uint32_t *)intaOffset) = (1u << 31u) | (glblEvt & 0xFFFFu);
    }
    else
    {
        *((uint32_t *)intaOffset) = 0;
    }
}

#if 0
static void App_setupPinmux()
{
    /* Setup GPIO 37 */
    *(volatile uint32_t *)0x11c094 = 0x50007 | (2 << 4);
    *(volatile uint32_t *)0x11c098 = 0x50007 | (2 << 4);
    *(volatile uint32_t *)0x11c09C = 0x50007 | (2 << 4);
}

static void App_initGpio()
{
    uint32_t chIdx, bitpos, gpio_id, bank_id;

    for (chIdx = 0; chIdx < APP_NUM_CH; chIdx ++)
    {
        gpio_id = GPIO_START + chIdx;
        bitpos = gpio_id % 32;
        bank_id = gpio_id / 16;

        *(volatile uint32_t *)0x00620044 = (1u << bitpos);
        *(volatile uint32_t *)0x00620038 &= ~(1u << bitpos);

        *(volatile uint32_t *)0x0062004C = (1u << bitpos);
        *(volatile uint32_t *)0x00620054 = (1u << bitpos);

        *(volatile uint32_t *)0x0062005C = (1u << bitpos);

        *(volatile uint32_t *)0x00620044 = (1u << bitpos);
        *(volatile uint32_t *)0x00620038 &= ~(1u << bitpos);

        *(volatile uint32_t *)0x00620008 = (1u << bank_id);

        *(volatile uint32_t *)0x0062004C = (1u << bitpos);
        *(volatile uint32_t *)0x00620054 = (1u << bitpos);
    }
}

static void App_setupGpioMuxIr()
{
    int32_t                             status;
    uint32_t                            chIdx;
    struct tisci_msg_rm_irq_set_req     rmIrqReq;
    struct tisci_msg_rm_irq_set_resp    rmIrqResp;

    memset(&rmIrqReq, 0x0, sizeof(rmIrqReq));
    memset(&rmIrqResp, 0x0, sizeof(rmIrqResp));

    rmIrqReq.valid_params           = 0U;
    rmIrqReq.global_event           = 0U;
    rmIrqReq.src_id                 = 0U;
    rmIrqReq.src_index              = 0U;
    rmIrqReq.dst_id                 = 0U;
    rmIrqReq.dst_host_irq           = 0U;
    rmIrqReq.ia_id                  = 0U;
    rmIrqReq.vint                   = 0U;
    rmIrqReq.vint_status_bit_index  = 0U;
    rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        rmIrqReq.src_id         = TISCI_DEV_GPIOMUX_INTRTR0;
        rmIrqReq.src_index      = GPIO_START + chIdx;

        /* Set the destination based on the core */
        rmIrqReq.dst_id         = TISCI_DEV_GPIOMUX_INTRTR0;
        rmIrqReq.dst_host_irq   = GPIOMUX_INTRTR0_OUTP_START_R5FSS0 + chIdx;

        /* Set the destination interrupt */
        rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
        rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;

        status = Sciclient_rmIrqSetRaw(
                   (const struct tisci_msg_rm_irq_set_req *)&rmIrqReq,
                    &rmIrqResp,
                    SCICLIENT_SERVICE_WAIT_FOREVER);

        if(status == CSL_PASS)
        {
            App_print ("Worked fine \n");
        }
        else
        {
            App_print ("Failed \n");
        }
    }
}

static void App_triggerGpio()
{
    uint32_t    chIdx;
    uint32_t    gpio_id;
    uint32_t    bitpos;
    static uint32_t iterCnt = 0;

    for (chIdx = 0; chIdx < APP_NUM_CH; chIdx ++)
    {
        gpio_id = GPIO_START + chIdx;
        bitpos = gpio_id % 32;

        if (iterCnt % 2 == 0)
        {
            /* Now set the data for both the GPIO,
               Both interrupts would be called,
               but in second loop on GPIO38 isr would be called */
            *(volatile uint32_t *)0x00620040 = (1u << bitpos);
        }
        else
        {
            /* Now set the data for both the GPIO,
               Both interrupts would be called,
               but in second loop on GPIO38 isr would be called */
            *(volatile uint32_t *)0x00620044 = (1u << bitpos);
        }
    }

    iterCnt ++;
}

#else
static void App_setupPinmux()
{
    *(volatile unsigned int *)(0x0011C0A4) = 0x50007; //CAP_FRS T23     GPIO0_41
    *(volatile unsigned int *)(0x0011C08C) = 0x50007; //CAP_FLS T25     GPIO0_35
    *(volatile unsigned int *)(0x0011C0B8) = 0x50007; //CAP_RRS AA24    GPIO0_46
    *(volatile unsigned int *)(0x0011C098) = 0x50007; //CAP_RLS V25     GPIO0_38

    *(volatile unsigned int *)(0x0011C084) = 0x50007; //CAP_FLC AA28    GPIO0_33
    *(volatile unsigned int *)(0x0011C09C) = 0x50007; //CAP_FRM T24     GPIO0_39
    *(volatile unsigned int *)(0x0011C0A8) = 0x50007; //CAP_FRC U24     GPIO0_42
    *(volatile unsigned int *)(0x0011C090) = 0x50007; //CAP_FLM W24     GPIO0_36

    *(volatile unsigned int *)(0x0011C088) = 0x50007; //CAP_RLC AD27    GPIO0_34
    *(volatile unsigned int *)(0x0011C0A0) = 0x50007; //CAP_RRM AB25    GPIO0_40
    *(volatile unsigned int *)(0x0011C0AC) = 0x50007; //CAP_RRC AC25    GPIO0_43
    *(volatile unsigned int *)(0x0011C094) = 0x50007; //CAP_RLM AA25    GPIO0_37
}

void App_initGpio()
{
    uint32_t chIdx, bitpos, gpio_id, bank_id;
    uint32_t offset = 0;

    for (chIdx = 0; chIdx < APP_NUM_CH; chIdx ++)
    {
        //gpio_id = GPIO_START + chIdx;
        gpio_id = gpio_input[chIdx];
        bitpos = gpio_id % 32;
        bank_id = gpio_id / 16;

        offset = gpio_id/32 * 0x28;

        /*GPIO_BINTEN*/
        //*(volatile uint32_t *)0x00600008 = (1u << bank_id);
        *(volatile uint32_t *)0x00600008 |= (1u << bank_id);

        /*GPIO_DIR*/
        *(volatile uint32_t *)(0x00600010+offset) &= ~(1u << bitpos);
        /*GPIO_SET_RIS_TRIG*/
        *(volatile uint32_t *)(0x00600024+offset) |= (1u << bitpos);
        /*GPIO_SET_FAL_TRIG*/
        *(volatile uint32_t *)(0x0060002c+offset) |= (1u << bitpos);
        /*GPIO_INTSTAT*/
        *(volatile uint32_t *)(0x00600034+offset) |= (1u << bitpos);

        //printf("[1] 0x00600008 = 0x%X\n", (1u << bank_id));
        //printf("[2] reg[0x%X] = 0x%X\n", (0x00600010+offset), (1u << bitpos));
        //printf("[3] reg[0x%X] = 0x%X\n", (0x00600024+offset), (1u << bitpos));
        //printf("[4] reg[0x%X] = 0x%X\n", (0x0060002c+offset), (1u << bitpos));
        //printf("[5] reg[0x%X] = 0x%X\n", (0x00600034+offset), (1u << bitpos));
    }
}
static void App_setupGpioMuxIr()
{
    int32_t                             status;
    uint32_t                            chIdx;
    struct tisci_msg_rm_irq_set_req     rmIrqReq;
    struct tisci_msg_rm_irq_set_resp    rmIrqResp;
    //int32_t i;

    memset(&rmIrqReq, 0x0, sizeof(rmIrqReq));
    memset(&rmIrqResp, 0x0, sizeof(rmIrqResp));

    rmIrqReq.valid_params           = 0U;
    rmIrqReq.global_event           = 0U;
    rmIrqReq.src_id                 = 0U;
    rmIrqReq.src_index              = 0U;
    rmIrqReq.dst_id                 = 0U;
    rmIrqReq.dst_host_irq           = 0U;
    rmIrqReq.ia_id                  = 0U;
    rmIrqReq.vint                   = 0U;
    rmIrqReq.vint_status_bit_index  = 0U;
    rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        rmIrqReq.src_id         = TISCI_DEV_GPIOMUX_INTRTR0;
        //rmIrqReq.src_index      = GPIO_START + chIdx;
        rmIrqReq.src_index      = gpio_input[chIdx];

        /* Set the destination based on the core */
        rmIrqReq.dst_id         = TISCI_DEV_GPIOMUX_INTRTR0;
        rmIrqReq.dst_host_irq   = GPIOMUX_INTRTR0_OUTP_START_R5FSS0 + chIdx;
        //rmIrqReq.dst_host_irq   = 16 + chIdx;
        //rmIrqReq.dst_host_irq   = 16;

        /* Set the destination interrupt */
        rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
        rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;

        printf("dst_host_irq=%d \n", rmIrqReq.dst_host_irq);
        status = Sciclient_rmIrqSetRaw(
                (const struct tisci_msg_rm_irq_set_req *)&rmIrqReq,
                &rmIrqResp,
                SCICLIENT_SERVICE_WAIT_FOREVER);

        if(status == CSL_PASS)
        {
            App_print ("Sciclient_rmIrqSetRaw Worked fine \n");
        }
        else
        {
            printf("Sciclient_rmIrqSetRaw Failed :%d\n", status);
        }
    }
}

static void App_triggerGpio()
{
    uint32_t    chIdx;
    uint32_t    gpio_id;
    uint32_t    bitpos;
    uint32_t    offset = 0;
    static uint32_t iterCnt = 0;

    for (chIdx = 0; chIdx < APP_NUM_CH; chIdx ++)
    {
        gpio_id = gpio_input[chIdx];
        //gpio_id = gpio_output[chIdx];
        bitpos = gpio_id % 32;
        offset = gpio_id/32 * 0x28;

        if (iterCnt % 2 == 0)
        {
            /* Now set the data for both the GPIO,
               Both interrupts would be called,
               but in second loop on GPIO38 isr would be called */
            //*(volatile uint32_t *)0x00620040 = (1u << bitpos);
            *(volatile uint32_t *)(0x00600018+offset)  = (1u << bitpos);
        }
        else
        {
            /* Now set the data for both the GPIO,
               Both interrupts would be called,
               but in second loop on GPIO38 isr would be called */
            //*(volatile uint32_t *)0x00620044 = (1u << bitpos);
            *(volatile uint32_t *)(0x0060001C+offset) = (1u << bitpos);
        }
    }

    iterCnt ++;
    //printf("iterCnt = %d \n", iterCnt);
}
#endif

static void App_print(const char *str)
{
    printf("%s", str);

    return;
}


static void App_cacheWb(const void *addr, int32_t size)
{
    CacheP_wb(addr, size);

    return;
}

static void App_cacheInv(const void * addr, int32_t size)
{
    CacheP_Inv(addr, size);

    return;
}

volatile uint32_t gWait = 0;
int32_t appGpioInit(void)
{
    /*Board_initCfg                       boardCfg;

    boardCfg = BOARD_INIT_PINMUX_CONFIG |
        BOARD_INIT_MODULE_CLOCK |
        BOARD_INIT_UART_STDIO | BOARD_INIT_UNLOCK_MMR |
        BOARD_INIT_PLL_MCU | BOARD_INIT_MODULE_CLOCK_MCU;

    Board_init(boardCfg);


    SET_DEVICE_STATE_ON(TISCI_DEV_GPIO0);
    //SET_DEVICE_STATE_ON(TISCI_DEV_GPIO1);
    SET_DEVICE_STATE_ON(TISCI_DEV_GPIO2);
    //SET_DEVICE_STATE_ON(TISCI_DEV_GPIO3);
    SET_DEVICE_STATE_ON(TISCI_DEV_GPIO4);
    //SET_DEVICE_STATE_ON(TISCI_DEV_GPIO5);
    SET_DEVICE_STATE_ON(TISCI_DEV_GPIO6);
    //SET_DEVICE_STATE_ON(TISCI_DEV_GPIO7);*/

    while (gWait);

    App_GpioDmaTest();

    return 0;
}

With this changes, i could clearly see GPIO toggling exactly at 10ms interval and capturing timestamp correctly. 

[MCU2_0] 12.816418 s: dst_host_irq=16
[MCU2_0] 12.816529 s: Sciclient_rmIrqSetRaw Worked fine
[MCU2_0] 14.806241 s: Enter ----------- App_eventDmaCb()
[MCU2_0] 14.816262 s: timer raw buf[1] = 2565245695---buf[0] = 2563317920
[MCU2_0] 14.816300 s: Diff 1927775
[MCU2_0] 14.816346 s: timer raw buf[2] = 2567244981---buf[1] = 2565245695
[MCU2_0] 14.816381 s: Diff 1999286
[MCU2_0] 14.816425 s: timer raw buf[3] = 2569244978---buf[2] = 2567244981
[MCU2_0] 14.816459 s: Diff 1999997
[MCU2_0] 14.816502 s: timer raw buf[4] = 2571244973---buf[3] = 2569244978
[MCU2_0] 14.816535 s: Diff 1999995
[MCU2_0] 14.816578 s: timer raw buf[5] = 2573244975---buf[4] = 2571244973
[MCU2_0] 14.816611 s: Diff 2000002
[MCU2_0] 14.816654 s: timer raw buf[6] = 2575244973---buf[5] = 2573244975
[MCU2_0] 14.816687 s: Diff 1999998
[MCU2_0] 14.816730 s: timer raw buf[7] = 2577244975---buf[6] = 2575244973
[MCU2_0] 14.816763 s: Diff 2000002
[MCU2_0] 14.816806 s: timer raw buf[8] = 2579244973---buf[7] = 2577244975
[MCU2_0] 14.816839 s: Diff 1999998
[MCU2_0] 14.816882 s: timer raw buf[9] = 2581244975---buf[8] = 2579244973
[MCU2_0] 14.816915 s: Diff 2000002
[MCU2_0] 14.816958 s: timer raw buf[10] = 2583244973---buf[9] = 2581244975
[MCU2_0] 14.816992 s: Diff 1999998
[MCU2_0] 14.817035 s: timer raw buf[11] = 2585244975---buf[10] = 2583244973
[MCU2_0] 14.817068 s: Diff 2000002
[MCU2_0] 14.817111 s: timer raw buf[12] = 2587244973---buf[11] = 2585244975
[MCU2_0] 14.817144 s: Diff 1999998
[MCU2_0] 14.817187 s: timer raw buf[13] = 2589244975---buf[12] = 2587244973
[MCU2_0] 14.817220 s: Diff 2000002
[MCU2_0] 14.817266 s: timer raw buf[14] = 2591244973---buf[13] = 2589244975
[MCU2_0] 14.817299 s: Diff 1999998
[MCU2_0] 14.817341 s: timer raw buf[15] = 2593244975---buf[14] = 2591244973
[MCU2_0] 14.817374 s: Diff 2000002
[MCU2_0] 14.817417 s: timer raw buf[16] = 2595244973---buf[15] = 2593244975
[MCU2_0] 14.817450 s: Diff 1999998
[MCU2_0] 14.817493 s: timer raw buf[17] = 2597244975---buf[16] = 2595244973
[MCU2_0] 14.817526 s: Diff 2000002
[MCU2_0] 14.817568 s: timer raw buf[18] = 2599244973---buf[17] = 2597244975
[MCU2_0] 14.817602 s: Diff 1999998
[MCU2_0] 14.817645 s: timer raw buf[19] = 2601244975---buf[18] = 2599244973
[MCU2_0] 14.817679 s: Diff 2000002
[MCU2_0] 14.817722 s: timer raw buf[20] = 2603244973---buf[19] = 2601244975
[MCU2_0] 14.817755 s: Diff 1999998
[MCU2_0] 14.817798 s: timer raw buf[21] = 2605244975---buf[20] = 2603244973
[MCU2_0] 14.817832 s: Diff 2000002
[MCU2_0] 14.817874 s: timer raw buf[22] = 2607244973---buf[21] = 2605244975
[MCU2_0] 14.817907 s: Diff 1999998
[MCU2_0] 14.817950 s: timer raw buf[23] = 2609244975---buf[22] = 2607244973
[MCU2_0] 14.817983 s: Diff 2000002
[MCU2_0] 14.818026 s: timer raw buf[24] = 2611244973---buf[23] = 2609244975
[MCU2_0] 14.818059 s: Diff 1999998
[MCU2_0] 14.818102 s: timer raw buf[25] = 2613244975---buf[24] = 2611244973
[MCU2_0] 14.818135 s: Diff 2000002
[MCU2_0] 14.818178 s: timer raw buf[26] = 2615244973---buf[25] = 2613244975
[MCU2_0] 14.818212 s: Diff 1999998
[MCU2_0] 14.818257 s: timer raw buf[27] = 2617244975---buf[26] = 2615244973
[MCU2_0] 14.818290 s: Diff 2000002
[MCU2_0] 14.818333 s: timer raw buf[28] = 2619244973---buf[27] = 2617244975
[MCU2_0] 14.818367 s: Diff 1999998
[MCU2_0] 14.818409 s: timer raw buf[29] = 2621244975---buf[28] = 2619244973
[MCU2_0] 14.818442 s: Diff 2000002
[MCU2_0] 14.818485 s: timer raw buf[30] = 2623244973---buf[29] = 2621244975
[MCU2_0] 14.818518 s: Diff 1999998
[MCU2_0] 14.818561 s: timer raw buf[31] = 2625244975---buf[30] = 2623244973
[MCU2_0] 14.818594 s: Diff 2000002
[MCU2_0] 14.818636 s: timer raw buf[32] = 2627244973---buf[31] = 2625244975
[MCU2_0] 14.818670 s: Diff 1999998
[MCU2_0] 14.818712 s: timer raw buf[33] = 2629244975---buf[32] = 2627244973
[MCU2_0] 14.818745 s: Diff 2000002
[MCU2_0] 14.818788 s: timer raw buf[34] = 2631244973---buf[33] = 2629244975
[MCU2_0] 14.818821 s: Diff 1999998
[MCU2_0] 14.818863 s: timer raw buf[35] = 2633244975---buf[34] = 2631244973
[MCU2_0] 14.818897 s: Diff 2000002
[MCU2_0] 14.818940 s: timer raw buf[36] = 2635244973---buf[35] = 2633244975
[MCU2_0] 14.818973 s: Diff 1999998
[MCU2_0] 14.819015 s: timer raw buf[37] = 2637244975---buf[36] = 2635244973
[MCU2_0] 14.819049 s: Diff 2000002
[MCU2_0] 14.819091 s: timer raw buf[38] = 2639244973---buf[37] = 2637244975
[MCU2_0] 14.819124 s: Diff 1999998
[MCU2_0] 14.819167 s: timer raw buf[39] = 2641244975---buf[38] = 2639244973
[MCU2_0] 14.819200 s: Diff 2000002
[MCU2_0] 14.819245 s: timer raw buf[40] = 2643244973---buf[39] = 2641244975
[MCU2_0] 14.819279 s: Diff 1999998
[MCU2_0] 14.819321 s: timer raw buf[41] = 2645244975---buf[40] = 2643244973
[MCU2_0] 14.819355 s: Diff 2000002
[MCU2_0] 14.819397 s: timer raw buf[42] = 2647244973---buf[41] = 2645244975
[MCU2_0] 14.819430 s: Diff 1999998
[MCU2_0] 14.819473 s: timer raw buf[43] = 2649244975---buf[42] = 2647244973
[MCU2_0] 14.819507 s: Diff 2000002
[MCU2_0] 14.819550 s: timer raw buf[44] = 2651244973---buf[43] = 2649244975
[MCU2_0] 14.819583 s: Diff 1999998
[MCU2_0] 14.819626 s: timer raw buf[45] = 2653244975---buf[44] = 2651244973
[MCU2_0] 14.819659 s: Diff 2000002
[MCU2_0] 14.819701 s: timer raw buf[46] = 2655244973---buf[45] = 2653244975
[MCU2_0] 14.819734 s: Diff 1999998
[MCU2_0] 14.819777 s: timer raw buf[47] = 2657244975---buf[46] = 2655244973
[MCU2_0] 14.819810 s: Diff 2000002
[MCU2_0] 14.819852 s: timer raw buf[48] = 2659244973---buf[47] = 2657244975
[MCU2_0] 14.819886 s: Diff 1999998
[MCU2_0] 14.819928 s: timer raw buf[49] = 2661244975---buf[48] = 2659244973
[MCU2_0] 14.819962 s: Diff 2000002
[MCU2_0] 14.820004 s: timer raw buf[50] = 2663244997---buf[49] = 2661244975
[MCU2_0] 14.820038 s: Diff 2000022
[MCU2_0] 14.820081 s: timer raw buf[51] = 2665244980---buf[50] = 2663244997
[MCU2_0] 14.820114 s: Diff 1999983
[MCU2_0] 14.820157 s: timer raw buf[52] = 2667244975---buf[51] = 2665244980
[MCU2_0] 14.820190 s: Diff 1999995
[MCU2_0] 14.820235 s: timer raw buf[53] = 2669244975---buf[52] = 2667244975
[MCU2_0] 14.820269 s: Diff 2000000
[MCU2_0] 14.820312 s: timer raw buf[54] = 2671244973---buf[53] = 2669244975
[MCU2_0] 14.820345 s: Diff 1999998
[MCU2_0] 14.820387 s: timer raw buf[55] = 2673244975---buf[54] = 2671244973
[MCU2_0] 14.820420 s: Diff 2000002
[MCU2_0] 14.820463 s: timer raw buf[56] = 2675244973---buf[55] = 2673244975
[MCU2_0] 14.820496 s: Diff 1999998
[MCU2_0] 14.820539 s: timer raw buf[57] = 2677244975---buf[56] = 2675244973
[MCU2_0] 14.820572 s: Diff 2000002
[MCU2_0] 14.820614 s: timer raw buf[58] = 2679244973---buf[57] = 2677244975
[MCU2_0] 14.820648 s: Diff 1999998
[MCU2_0] 14.820690 s: timer raw buf[59] = 2681244975---buf[58] = 2679244973
[MCU2_0] 14.820724 s: Diff 2000002
[MCU2_0] 14.820766 s: timer raw buf[60] = 2683244973---buf[59] = 2681244975
[MCU2_0] 14.820800 s: Diff 1999998
[MCU2_0] 14.820843 s: timer raw buf[61] = 2685244975---buf[60] = 2683244973
[MCU2_0] 14.820876 s: Diff 2000002
[MCU2_0] 14.820919 s: timer raw buf[62] = 2687244973---buf[61] = 2685244975
[MCU2_0] 14.820952 s: Diff 1999998
[MCU2_0] 14.820994 s: timer raw buf[63] = 2689244975---buf[62] = 2687244973
[MCU2_0] 14.821027 s: Diff 2000002
[MCU2_0] 14.821070 s: timer raw buf[64] = 2691244973---buf[63] = 2689244975
[MCU2_0] 14.821104 s: Diff 1999998
[MCU2_0] 14.821146 s: timer raw buf[65] = 2693244975---buf[64] = 2691244973
[MCU2_0] 14.821180 s: Diff 2000002
[MCU2_0] 14.821225 s: timer raw buf[66] = 2695244973---buf[65] = 2693244975
[MCU2_0] 14.821260 s: Diff 1999998
[MCU2_0] 14.821303 s: timer raw buf[67] = 2697244975---buf[66] = 2695244973
[MCU2_0] 14.821336 s: Diff 2000002
[MCU2_0] 14.821379 s: timer raw buf[68] = 2699244973---buf[67] = 2697244975
[MCU2_0] 14.821412 s: Diff 1999998
[MCU2_0] 14.821454 s: timer raw buf[69] = 2701244975---buf[68] = 2699244973
[MCU2_0] 14.821487 s: Diff 2000002
[MCU2_0] 14.821530 s: timer raw buf[70] = 2703244973---buf[69] = 2701244975
[MCU2_0] 14.821563 s: Diff 1999998
[MCU2_0] 14.821606 s: timer raw buf[71] = 2705244975---buf[70] = 2703244973
[MCU2_0] 14.821639 s: Diff 2000002
[MCU2_0] 14.821682 s: timer raw buf[72] = 2707244973---buf[71] = 2705244975
[MCU2_0] 14.821715 s: Diff 1999998
[MCU2_0] 14.821758 s: timer raw buf[73] = 2709244975---buf[72] = 2707244973
[MCU2_0] 14.821792 s: Diff 2000002
[MCU2_0] 14.821835 s: timer raw buf[74] = 2711244973---buf[73] = 2709244975
[MCU2_0] 14.821869 s: Diff 1999998
[MCU2_0] 14.821912 s: timer raw buf[75] = 2713244975---buf[74] = 2711244973
[MCU2_0] 14.821946 s: Diff 2000002
[MCU2_0] 14.821989 s: timer raw buf[76] = 2715244973---buf[75] = 2713244975
[MCU2_0] 14.822022 s: Diff 1999998
[MCU2_0] 14.822065 s: timer raw buf[77] = 2717244975---buf[76] = 2715244973
[MCU2_0] 14.822098 s: Diff 2000002
[MCU2_0] 14.822141 s: timer raw buf[78] = 2719244973---buf[77] = 2717244975
[MCU2_0] 14.822175 s: Diff 1999998
[MCU2_0] 14.822241 s: Diff 2000002

Regards,

Brijesh

Hi, Brijesh

If I use the following configuration, initialization will fail.
code
uint32_t INTR_OFFSET = 0u;
#define GPIOMUX_INTRTR0_OUTP_START_R5FSS0 (16 + INTR_OFFSET)

log：
[MCU2_1] 12.592137 s: Sciclient_rmIrqSetRaw Failed :-1

Did you modify RM? Can you send me the RM file you modified?

Hi Vinter,

Yes, this requires change in the RM. Can you please try with the attached tiboot3.bin file? This will allow you to use at max 4 GPIO. If you require more than 4 GPIO, RM requires to be changed. 

/cfs-file/__key/communityserver-discussions-components-files/791/4162.tiboot3.zip

Also please find attached modified rm.c file. 

/cfs-file/__key/communityserver-discussions-components-files/791/4336.rm_2D00_cfg.c

Regards,

Brijesh

Hi, Brijesh

1. Unable to boot on our board using your "tiboot3. bin" file;

2. Using your 'rm cfg. c' file to run will still result in errors:
[MCU2_1] 12.615456 s: chIdx:0 UDMA channel open sucess!
[MCU2_1] 12.615614 s: chIdx:0 UDMA TX channel config sucess!
[MCU2_1] 12.615763 s: chIdx:0 UDMA RX channel config sucess!
[MCU2_1] 12.616111 s: dst_host_irq=16
[MCU2_1] 12.616182 s: Sciclient_rmIrqSetRaw Failed :-1

Could you please help confirm that there are no other modifications?

Also, can you send me both the modified "rm cfg. c" and "j721s2 evm. syscfg" files?

Thank you~！

Hi Vinter,

oh sorry, i tried it on mcu2_0. For mcu2_1, you might have to change INTR_OFFSET macro in the application. Each R5F has 4 GPIO interrupts allocated, so first 16 to 19 are allocated to mcu2_0. You can try using 20 to 23 output interrupts for mcu2_1.

or can you try first on mcu2_0?

Regards,

Brijesh 

Hi, Brijesh

Yes, I can now capture the timestamp.

But I have a question: How can I use the sysconfig tool to modify the "start_resource" in the "rm cfg. c" file? I can only modify ”num_resource“ using the sysconfig tool here. Is it my tool version issue?

Can you also send me your modified "j721s2 evm. syscfg" file?

Thank you~！

Hi Vinter,

That's the limitation in the current sysconfig tool. There is no way to specify the start resource id for these resources, so we have to update it manually. 

I have raised to the team.

Regards,

Brijesh

Hi, Brijesh

Ok, I'll manually modify it.

I have two questions:

1. How did you confirm that mcu2-1 "start_resource" is incorrect? I would like to know the confirmation method.

2. How is the value of "gIntAggrLeviEvtId" confirmed in the "app_gpio_dma. c" file? I also want to know the confirmation method.

static volatile uint32_t gIntAggrLeviEvtId[16] = {
116, 117, 118, 119, 120, 121, 122, 123,
124, 125, 126, 127, 128, 129, 130, 131};

Above, thank you~!

Hi Vinter,

I just referred to rm-cfg.c file and below link. rm-cfg.c file says GPIOMUX output for mcu2_1 starts from offset 3 and has 4 num_resources. 

J721S2 Interrupt Management Device Descriptions — TISCI User Guide

Regarding second question, refer to above link. output 16 from GPIO mux goes as input 116 for intaggr_levi_pend. This is what is connected to the UDMA.

Regards,

Brijesh

Hi, Brijesh

Please help answer a question: Why is the difference between the first and second timestamps not accurate, not 10ms but 9.3ms (this problem exists whether using polling or interrupts)

log:
[MCU2_1] 49.707735 s: timer raw buf[1] = 11929424026---buf[0] = 11927075770
[MCU2_1] 49.707773 s: Diff 2348256
[MCU2_1] 49.707824 s: timer raw buf[2] = 11931923352---buf[1] = 11929424026
[MCU2_1] 49.707861 s: Diff 2499326
[MCU2_1] 49.707911 s: timer raw buf[3] = 11934423282---buf[2] = 11931923352
[MCU2_1] 49.707949 s: Diff 2499930
[MCU2_1] 49.708001 s: timer raw buf[4] = 11936923234---buf[3] = 11934423282
[MCU2_1] 49.708038 s: Diff 2499952
[MCU2_1] 49.708088 s: timer raw buf[5] = 11939423272---buf[4] = 11936923234
[MCU2_1] 49.708125 s: Diff 2500038
[MCU2_1] 49.708175 s: timer raw buf[6] = 11941923232---buf[5] = 11939423272
[MCU2_1] 49.708213 s: Diff 2499960
[MCU2_1] 49.708264 s: timer raw buf[7] = 11944423232---buf[6] = 11941923232
[MCU2_1] 49.708302 s: Diff 2500000
[MCU2_1] 49.708353 s: timer raw buf[8] = 11946923232---buf[7] = 11944423232
[MCU2_1] 49.708391 s: Diff 2500000

Hi Vinter,

May be GPIO is toggled early for the first time, or the wait between two GPIO toggle was not sufficient, or probably sleed did not work correctly for the first time.

Regards,

Brijesh

Hi, Brijesh

Ok, let me confirm the GPIO and waiting time first.
Also, the attachment is the RM file that I modified. Can you help me check if there are any issues with the modifications?

Thank you~!

6204.rm-cfg.c

Hi Vinter,

Yes, as such, it looks fine. You have allocated 4 interrupt to mcu2_0 and 12 interrupts to mcu2_1 and rest to the other cores. Since you are using mcu2_1, please also make sure to use irq offset at 16 + 4. 

Regards,

Brijesh

Hi, Brijesh

I have also reassigned DMA resources in RM, and this allocation is also okay, right?

Hi Vinter,

Yes, it looks fine to me.

Regards,

Brijesh