Hi There,
I want to used the IEP timer with its interrupt capability. I have configured the timer and verified. The timer is running properly(individually), but when i tried to enable its interrupt. The timer stops working. I have attached the code. can anybody help me.
#include <stdint.h>
#include <pru_cfg.h>
#include <pru_intc.h>
#include <pru_iep.h>
#include "resource_table_empty.h"
volatile pruCfg CT_CFG __attribute__((cregister("PRU_CFG", near), peripheral));
volatile uint32_t *ddr_var = (uint32_t *)0x90000000;
volatile register uint32_t __R30;
volatile register uint32_t __R31;
uint32_t temp = 0;
void main(void)
{
/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
//-------------------------------------------------------------------------------
CT_INTC.SIPR0 = 0x0000000F;
CT_INTC.SIPR1 = 0;
CT_INTC.SITR0 = 0;
CT_INTC.SITR1 = 0;
CT_INTC.CMR1 = 0x01000000;
CT_INTC.HMR0 = 0x00000100;
// Clear the status of all interrupts
CT_INTC.SECR0 = 0xFFFFFFFF;
CT_INTC.SECR1 = 0xFFFFFFFF;
CT_INTC.HIEISR = 0x00000001;
//-------------------------------------------------------------------------------
/* Disable counter */
CT_IEP.TMR_GLB_CFG_bit.CNT_EN = 0;
/* Reset Count register */
CT_IEP.TMR_CNT = 0x0;
/* Clear overflow status register */
CT_IEP.TMR_GLB_STS_bit.CNT_OVF = 0x1;
/* Set compare value */
CT_IEP.TMR_CMP0 = 0x50000000;
/* Clear compare status */
CT_IEP.TMR_CMP_STS_bit.CMP_HIT = 0xFF;
/* Disable compensation */
CT_IEP.TMR_COMPEN_bit.COMPEN_CNT = 0x0;
/* Enable CMP0 and reset on event */
CT_IEP.TMR_CMP_CFG_bit.CMP0_RST_CNT_EN = 0x1;
CT_IEP.TMR_CMP_CFG_bit.CMP_EN = 0x1;
//CT_INTC.SECR0 = 0xFFFFFFFF;
//CT_INTC.SECR1 = 0xFFFFFFFF;
CT_INTC.ECR0 = 0xFFFFFFFF;
CT_INTC.ECR1 = 0xFFFFFFFF;
CT_INTC.ESR0 = 0x00000080;
CT_INTC.ESR1 = 0x00000000;
CT_INTC.GER = 1;
#define PIN 1
// set all GPIOs low
//__R30 = 0x0;
/* Enable counter */
CT_IEP.TMR_GLB_CFG = 0x11;
/* Poll until R31.31 is set */
do {
while ((__R31 & 0x80000000) == 0) {
*ddr_var = CT_IEP.TMR_CNT;
}
/* Verify that the IEP is the source of the interrupt */
} while ((CT_INTC.SECR0 & (1 << 7)) == 0);
//toggle
//__R30 ^= 1UL << PIN;
//*ddr_var = temp++;
/* Disable counter */
CT_IEP.TMR_GLB_CFG_bit.CNT_EN = 0x0;
/* Disable Compare0 */
CT_IEP.TMR_CMP_CFG = 0x0;
/* Clear Compare status */
CT_IEP.TMR_CMP_STS = 0xFF;
/* Clear the status of the interrupt */
CT_INTC.SECR0 = (1 << 7);
/* Halt the PRU core */
__halt();
//while(1);
}