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I2C Back-to-Back Transfers

Takahiro Ogo
Genius 5940 points

Hi,
I want to confirm a I2C programing. (I'm using 6748/L138)

I saw the I2C tips wiki page.
http://processors.wiki.ti.com/index.php/I2C_Tips
I have one question about "Back-to-Back Transfers" on this page.

if we do multiple transfers in a row by I2C,
- We must have some amount of delay between the transfers.
or We must poll for I2CMDR.MST=0 before you attempt to initiate the next START condition.


Am I right?
This specifications, I didn't find it in I2C UG. Also, A sample code of EVM didn't care in this specs. Why?

Thanks in advance for your help.
-Takao

 

  • 0
    Genius 5940 points

    Hi,
    I'm waiting for reply. Can someone please give me advice? 

    Takao

  • 0
    TI__Guru*** 125430 points

    Takao said:

    if we do multiple transfers in a row by I2C,
    - We must have some amount of delay between the transfers.
    or We must poll for I2CMDR.MST=0 before you attempt to initiate the next START condition.

    Correct -- you could potentially set it up such at the start of the transfer, e.g. right after polling for BB.  That way in the case of only a single transfer (or naturally spaced transfers) you don't have to wait for the bit to clear and only in the case of back-to-back transfer would the code spend any time polling for MST==0.

     

    Takao said:
    This specifications, I didn't find it in I2C UG. Also, A sample code of EVM didn't care in this specs. Why?

    I've made suggestions to improve the documentation but it was never implemented.  I wrote the wiki page to capture some of these finer details.

  • 0 in reply to Brad Griffis
    Genius 5940 points

    Hi,
    Thank you for giving me the reply and useful wiki page !

    My customer was able to solve i2c problem, thanks to you.
    -Takao