Hi
We are using the MityDSP platform from Critical Link. On this platform a NAND flash and a FPGA are connected to the EMIFA of the OMAP.
The NAND flash is only used on the ARM (flash file system) and we will from the DSP side be accessing the FPGA both by direct memory access and by using the EDMA3 controller (the FPGA will be loaded from ARM side). The EDMA3 transfers; FPGA<->DSP IRAM will happen frequently, perhaps at a 10khz rate or faster.We would very much like to prioritize this traffic over ANYTHING else. I am using the EDMA3 LLD.
We are aware of other communication options between the FPGA and OMAP, for instance we have the UPP available as well. But currently we would prefer the FPGA to be memory mapped.
I have been looking at the EDMA priority settings in the current setup we are running.
From the EDMA priority settings below (which I just dumped directly from the registers)
MSTPRI0 = 0x44442222
MSTPRI1 = 0x44440000
MSTPRI2 = 0x54604404
It seems EDMA3_0 TC0 and TC1 has the highest priority (over EDMA3_1).
I am using the EDMA3 LLD driver on queue 0.
I assume Queue 0 is EDMA3_0_TC0, queue 1 is EDMA3_0_TC1, queue 2 is EDMA3_1_TC0?
Is this correct?
What I need is to give EDMA3 higher priority on the EMIFA interface than NAND flash access (or anything else).
What I can see from the above EDMA3 priority settings, this seems already to be the case.
What I am trying to figure out is how the NAND Flash Controller/Linux driver is using the EMIFA interface.
Is there anything else I can tweak to be sure that the NAND controller/driver has lower priority than EDMA3 on the EMIFA?
We will at times in our system be dumping a file (to flash) which contains a large amount of data (>MB) received from the DSP. This will of course cause many writes to the NAND flash, so we would very much like to keep each NAND access as quick as possible.
Any suggestions are highly appriciated.
Many thanks,
Mads
