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DM6467T, PCI Interrupt configuration

Jimmy Fung
Intellectual 575 points

I'm trying to get PCI interrupts to work.  I've looked at this web page:

http://processors.wiki.ti.com/index.php/PCI_Interrupt_Handling_on_DM6467/DM6467T_PCI_Host  

 

There is a bug in this line:

set_irq_type(gpio_to_irq(48), IRQ_TYPE_EDGE_RISING);

 

I think it should be gpio_to_irq(0), or just the plain literal 48

(which I'm using).

 

Also, one apparently needs to configure the GPIO register SET_FAL_TRIG01 so that an interrupt will be generated; this is not mentioned anywhere on the web page.  After doing this I can see the interrupt count increase to a value greater than zero in /proc/interrupts if I manually short-circuit the pulled-up GPIO0 to ground; the PCI bridge is not yet generating interrupts by itself, but this could be a separate problem.

 

My question: is this appropriate for PCI interrupts, which are level-based?  There's apparently no support for level-based interrupts in the GPIO peripheral, so I'm worried that there will be lost

interrupts or other problems.

  • 0
    TI__Expert 5685 points

    Hello,

    Please check latest http://processors.wiki.ti.com/index.php/PCI_Interrupt_Handling_on_DM6467/DM6467T_PCI_Host#Setting_up_GPIO_Interrupts this section is updated already with correct argument to gpio_to_irq().

    As for configuring SET_FAL_TRIG01, I think that will be conflicting since the document already mentions using IRQ_TYPE_EDGE_RISING for GPIO irq which should in turn set corresponding rising trigger register in GPIO (assuming the PCI device generates a high level for interrupt).
     
    Also, I don't think there will be any missing interrupt due to level --> edge combination with GPIO if roughly following steps are taken in GPIO and PCI interrupt handlers (just listed important steps to avoid interrupt miss):
     
    GPIO handler:
    1) clear interrupt status in GPIO - this means any new high level transition on PCI interrupt line will set GPIO interrupt status
    2) Call PCI interrupt handler
    3) Once returned, check the GPIO interrupt status again
     
    PCI handler:
    1) clear interrupt and handle interrupt condition (or schedule a handler)
    2) indicate end of interrupt / re-enable interrupt on handling

    Let me know if you see any gaps.

       Hemant