About Receiving Audio Signal By Mcbsp

qinbin wang

Other Parts Discussed in Thread: OMAPL138

hello,

My board type is omapl138,recently i write a driver for receiving audio signal,i can get the signal and i print it in my callback function,find it is right.The problem is the linux system only do the receiving signal job forever,even the linux order such as ifconfig ls ping etc. doesn't work,it seems system is dead.I cann't use ssh to connect the system neither,other times it can.I write a cycle function just for testing whether the system is dead.If i do not start mcbsp and edma(receiving signal),system is alive.So i judge when i start mcbsp,the CPU doesn't work for linux or it is interrupted forever or something else,could you show me how to deal with such problem.

My driver is based on edma_test.c、mcbsp_test.c、Chaithrika's mcbsp.c and ti's dma.c. My linux kernel type is psp\linux-2.6.33-rc4-psp03.20.00.14.

I am waiting for you,thanks! たすけてください.

/***********************************************************************************************************************/

My jibunno_usr.c is like:

#include <stdio.h>
#include <string.h>
#include <unistd.h>
#include <fcntl.h>
#include <errno.h>
#include <termios.h>
#include <sys/ioctl.h>
#include <resolv.h>
#include <pthread.h>

int fd_mcbsp;

int main(int argc, char * argv[])
{
system("mknod /dev/jibunno_drv c 233 0");
fd_mcbsp = open("/dev/jibunno_drv", O_RDWR | O_SYNC );

if (fd_mcbsp == -1)
    printf("mcbsp_usr:open_mcbsp: Unable to open /dev/mcbsp_control_char \n");
else
   printf("mcbsp_usr:open_mcbsp: open /dev/mcbsp_control_char success \n");

ioctl(fd_mcbsp,21,0);
ioctl(fd_mcbsp,11,0);
ioctl(fd_mcbsp,1,0);

return 0;
}

/***********************************************************************************************************************/

My jibunno_drv.c is like:

#include <linux/module.h>
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/moduleparam.h>
#include <linux/sysctl.h>
#include <linux/mm.h>
#include <linux/dma-mapping.h>
#include <linux/delay.h>

#include <mach/memory.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/edma.h>
#include <mach/mcbsp.h>

#include <linux/sched.h>
#include <asm/uaccess.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/gfp.h>
#include <linux/cdev.h>
#include <linux/sched.h>
#include <linux/proc_fs.h>

#include <linux/delay.h>

MODULE_LICENSE("GPL");
#define YIMA_VERSION "2011.07.20.V-05"

static volatile short irqraised1 = 0;
static volatile short irqraised2 = 0;

/* Register offset macros */
#define MCBSP_DRR (0x00)
#define MCBSP_DXR (0x04)
#define MCBSP_SPCR (0x08)
#define MCBSP_RCR (0x0C)
#define MCBSP_XCR (0x10)
#define MCBSP_SRGR (0x14)
#define MCBSP_MCR (0x18)
#define MCBSP_RCER0 (0x1C)
#define MCBSP_XCER0 (0x20)
#define MCBSP_PCR (0x24)
#define MCBSP_RCER1 (0x28)
#define MCBSP_XCER1 (0x2C)
#define MCBSP_RCER2 (0x30)
#define MCBSP_XCER2 (0x34)
#define MCBSP_RCER3 (0x38)
#define MCBSP_XCER3 (0x3C)
#define MCBSP_WFIFOCTL (0x810)
#define MCBSP_WFIFOSTS (0x814)
#define MCBSP_RFIFOCTL (0x818)
#define MCBSP_RFIFOSTS (0x81C)

/* Register bit definitions */
/* SPCR */
#define FRST        BIT(23)
#define GRST        BIT(22)
#define XINTM_MASK    (BIT(21) | BIT(20))
#define XSYNCERR    BIT(19)
#define XEMPTY        BIT(18)
#define XRDY        BIT(17)
#define    XRST        BIT(16)
#define DLB        BIT(15)
#define RJUST_MASK    (BIT(14) | BIT(13))
#define CLKSTP_MASK    (BIT(12) | BIT(11))
#define DXENA        BIT(7)
#define    RINTM_MASK    (BIT(5) | BIT(4))
#define RSYNCERR    BIT(3)
#define RFULL        BIT(2)
#define RRDY        BIT(1)
#define RRST        BIT(0)

#define    RINTM(value)    (value << 4)
#define CLKSTP(value)    (value << 11)
#define RJUST(value)    (value << 13)
#define XINTM(value)    (value << 20)

/* PCR */

#define FSXM        BIT(11)
#define FSRM        BIT(10)
#define CLKXM        BIT(9)
#define CLKRM        BIT(8)
#define SCLKME        BIT(7)
#define FSXP        BIT(3)
#define FSRP        BIT(2)
#define CLKXP        BIT(1)
#define CLKRP        BIT(0)

/* RCR / XCR */

#define PHASE        BIT(31)
#define FRLEN2(value)    (value << 24)
#define WDLEN2(value)    (value << 21)
#define COMPAND(value)    (value << 19)
#define FIG        BIT(18)
#define DATDLY(value)    (value << 16)
#define FRLEN1(value)    (value << 8)
#define WDLEN1(value)    (value << 5)
#define WDREVRS        BIT(4)

/* SRGR */

#define GSYNC        BIT(31)
#define CLKSP        BIT(30)
#define CLKSM        BIT(29)
#define    FSGM        BIT(28)
#define    FPER(value)    (value << 16)
#define    FWID(value)    (value << 8)
#define CLKGDV(value)    (value)
#define CLKGDV_MASK    (0xff)

/* MCR */

#define XMCME        BIT(25)
#define XPBBLK(value)    (value << 23)
#define XPABLK(value)    (value << 21)
#define XCBLK        (BIT(20) | BIT(19) | BIT(18))
#define XMCM(value)    (value << 16)
#define RMCME        BIT(9)
#define RPBBLK(value)    (value << 7)
#define RPABLK(value)    (value << 5)
#define RCBLK        (BIT(4) | BIT(3) | BIT(2))
#define RMCM        BIT(0)
#define XMCM_MASK    (BIT(16) | BIT(17))

/* WFIFOCTL / RFIFOCTL */
#define FIFOEN        BIT(16)
#define NUMEVT(value)    (value << 8)
#define NUMDMA(value)    (value)
#define NUMEVT_MASK    (0xff << 8)
#define NUMDMA_MASK    0xff

/* WFIFOSTS / RFIFOSTS */
#define LVL_MASK 0xff

struct file_operations mcbsp_drv_fops;
#define MCBSP_DRV_MAJOR 233

#define TCINTEN_SHIFT               20
#define ITCINTEN_SHIFT              21
#define TCCHEN_SHIFT                22
#define ITCCHEN_SHIFT               23

#define RCINTEN_SHIFT 4
#define IRCINTEN_SHIFT 5

#define BUFFSIZE 4

static dma_addr_t physdest1 = 0;
static dma_addr_t physdest2 = 0;

static char *bufdest1 = NULL;
static char *bufdest2 = NULL;

static unsigned int dma_ch1 = 0;
static unsigned int dma_ch2 = 0;
static unsigned int dma_ch3 = 0;
static struct davinci_mcbsp_dev *dev = NULL;

static int device_id = 0;
static int buf_size = (1 * 1024);
static int buf_fmt = 0;
static int num_pkts = 1;
static int word_len = 4;
static int frame_len = 7;
static bool dlb = 0;
static int numevt = 0;
static int mc_mode = 0;
static int master = 0;
static int data_delay = 2;

static void printWelcomeBanner(void)
{
printk("***************************************************************\n\r");
printk("*                                                             *\n\r");
printk("*                            ****                             *\n\r");
printk("*                            ****                             *\n\r");
printk("*                            ******o***                       *\n\r");
printk("*                      ********_///_****                      *\n\r");
printk("*                      ***** /_//_/ ****                      *\n\r");
printk("*                       ** ** (__/ ****                       *\n\r");
printk("*                           *********                         *\n\r");
printk("*                            ****                             *\n\r");
printk("*                            ***                              *\n\r");
printk("*                                                             *\n\r");
printk("*                     TI EDMA3 LOW LEVEL DRIVER               *\n\r");
printk("*                                                             *\n\r");
printk("*                                                             *\n\r");
printk("*       For issues on TI EDMA3 LLD, contact TII PSP Team      *\n\r");
printk("*                                                             *\n\r");
printk("*                                                             *\n\r");
printk("*                                                             *\n\r");
printk("***************************************************************\n\r");
printk("\r\n\r\n");
}

static void just_do_the_while(void)
{
int i;
for(i=0;i<30;i++)
{
mdelay(500);
printk("just_do_the_while delay ii=%d\n",i);
}
}

int mcbsp_dma_stop_rx(struct davinci_mcbsp_dev *dev)
{
edma_stop(dma_ch1);
edma_free_channel(dma_ch1);

edma_stop(dma_ch2);
edma_free_slot(dma_ch2);
edma_free_channel(dma_ch2);
edma_stop(dma_ch3);
edma_free_slot(dma_ch3);
edma_free_channel(dma_ch3);

dma_free_coherent(NULL, BUFFSIZE, bufdest1,physdest1);
dma_free_coherent(NULL, BUFFSIZE, bufdest2,physdest2);
return 0;
}

static void mcbsp_dma_rx_callback(unsigned lch, u16 ch_status, void *data)
{
int i = 0;
switch(ch_status) {
case DMA_COMPLETE:
  printk ("From Callback 1: Channel %d status is: %u\n",lch, ch_status);
  for(i = 0; i < BUFFSIZE; i++){
   printk("%02x ",bufdest1[i]);
  }
  printk("\n");
  for(i = 0; i < BUFFSIZE; i++){
   printk("%02x ",bufdest2[i]);
  }
  printk("\n\n\n");
  irqraised1 = 1;
  break;
case DMA_CC_ERROR:
  printk ("\nFrom Callback 1: DMA_CC_ERROR occured " "on Channel %d status is: %u\n", lch, ch_status);
  irqraised1 = -1;
  break;
default:
  printk ("\nFrom Callback 2: DMA_CC_ERROR occured on Channel %d status is: %u\n", lch, ch_status);
  break;
}
}

int mcbsp_dma_start_rx(struct davinci_mcbsp_dev *dev)
{
int result = 0;
int acnt = 1;
int bcnt = 4;
int ccnt = 1;

unsigned int BRCnt = 0;
int srcbidx = 0;
int desbidx = 0;
int srccidx = 0;
int descidx = 0;
struct edmacc_param param_set;

BRCnt = 4;
srcbidx = 0;
desbidx = 1;
srccidx = 0;
descidx = -3;

bufdest1 = dma_alloc_coherent (NULL, BUFFSIZE,&physdest1, 0);
if (!bufdest1)
{
printk("dma_alloc_coherent failed for physdest1\n");
return -ENOMEM;
}

bufdest2 = dma_alloc_coherent (NULL, BUFFSIZE,&physdest2, 0);
if (!bufdest2)
{
  printk ("dma_alloc_coherent failed for physdest2\n");
  dma_free_coherent(NULL, BUFFSIZE, bufdest1,physdest1);
  return -ENOMEM;
}

result = edma_alloc_channel (dev->rx_params.dma_ch, mcbsp_dma_rx_callback, dev, EVENTQ_0);
if (result < 0)
{
printk ("edma3_memtomemcpytest_dma_link::edma_alloc_channel failed for dma_ch1, error:%d\n", result);
return result;
}

dma_ch1 = result;
edma_set_src (dma_ch1, (unsigned long)(dev->rx_params.dma_addr), INCR, W8BIT);
edma_set_dest (dma_ch1, (unsigned long)(physdest1), INCR, W8BIT);
edma_set_src_index (dma_ch1, srcbidx, srccidx);
edma_set_dest_index (dma_ch1, desbidx, descidx);
edma_set_transfer_params (dma_ch1, acnt, bcnt, ccnt, BRCnt, ASYNC);

edma_read_slot (dma_ch1, &param_set);
param_set.opt |= (1 << ITCINTEN_SHIFT);
param_set.opt |= (1 << TCINTEN_SHIFT);
param_set.opt |= EDMA_TCC(EDMA_CHAN_SLOT(dma_ch1));
edma_write_slot(dma_ch1, &param_set);

result = edma_alloc_slot (0, EDMA_SLOT_ANY);
if (result < 0)
{
printk ("\nedma3_memtomemcpytest_dma_link::edma_alloc_slot failed for dma_ch2, error:%d\n", result);
return result;
}
dma_ch2 = result;
edma_set_src (dma_ch2, (unsigned long)(dev->rx_params.dma_addr), INCR, W8BIT);
edma_set_dest (dma_ch2, (unsigned long)(physdest2), INCR, W8BIT);
edma_set_src_index (dma_ch2, srcbidx, srccidx);
edma_set_dest_index (dma_ch2, desbidx, descidx);
edma_set_transfer_params (dma_ch2, acnt, bcnt, ccnt, BRCnt, ASYNC);

edma_read_slot (dma_ch2, &param_set);
param_set.opt |= (1 << ITCINTEN_SHIFT);
param_set.opt |= (1 << TCINTEN_SHIFT);
param_set.opt |= EDMA_TCC(EDMA_CHAN_SLOT(dma_ch1));
edma_write_slot(dma_ch2, &param_set);

result = edma_alloc_slot (0, EDMA_SLOT_ANY);
if (result < 0)
{
printk ("\nedma3_memtomemcpytest_dma_link::edma_alloc_slot failed for dma_ch3, error:%d\n", result);
return result;
}
dma_ch3 = result;
edma_set_src (dma_ch3, (unsigned long)(dev->rx_params.dma_addr), INCR, W8BIT);
edma_set_dest (dma_ch3, (unsigned long)(physdest1), INCR, W8BIT);
edma_set_src_index (dma_ch3, srcbidx, srccidx);
edma_set_dest_index (dma_ch3, desbidx, descidx);
edma_set_transfer_params (dma_ch3, acnt, bcnt, ccnt, BRCnt, ASYNC);

edma_read_slot (dma_ch3, &param_set);
param_set.opt |= (1 << ITCINTEN_SHIFT);
param_set.opt |= (1 << TCINTEN_SHIFT);
param_set.opt |= EDMA_TCC(EDMA_CHAN_SLOT(dma_ch1));
edma_write_slot(dma_ch3, &param_set);

edma_link(dma_ch1, dma_ch2);
edma_link(dma_ch2, dma_ch3);
edma_link(dma_ch3, dma_ch2);
edma_start(dma_ch1);

return result;
}

static int __init mcbsp_drv_init(void)
{
int ret,i;
int reg_read_pinmux0;

printk("\nStarting McBSP test\n");
printk("******Hello,Kitty******\n\n");
printk("****** VERSION:%s ******\n\n",YIMA_VERSION);
printk("\nmcbsp_drv registering init start... \n");
ret = register_chrdev(MCBSP_DRV_MAJOR,"mcbsp_drv",&mcbsp_drv_fops);
if (ret < 0)
{
     printk("Error registering mcbsp_drv device \n");
     return ret;
}

printk ("mcbsp_drv: registering module successfuly! \n");
davinci_mcbsp_request(device_id, &dev);
//just_do_the_while();
return 0;
}

static int __exit mcbsp_drv_exit(void)
{
   unregister_chrdev(MCBSP_DRV_MAJOR,"mcbsp_drv");
  davinci_mcbsp_stop_rx(dev);
  mcbsp_dma_stop_rx(dev);
  davinci_mcbsp_free(device_id);
  printk("McBSP test done... exiting\n");

  return 0;
}

static ssize_t mcbsp_drv_read(struct file *file, char __user *buf,size_t count,loff_t *ppos)
{
printk("mcbsp_drv_read \n");
return 0;
}

static ssize_t mcbsp_drv_write(struct file *file1,const char __user *buf,size_t count,loff_t *ppos)
{
printk("mcbsp_drv_write \n");
return 0;
}

static int mcbsp_drv_open (struct inode *inode,struct file *file)
{
printk("mcbsp_drv device open \n");
return 0;
}

static int mcbsp_drv_release (struct inode *inode,struct file *file)
{
printk("mcbsp_drv_release \n");
    return 0;
    printk("mcbsp_drv device release \n");
    davinci_mcbsp_free(device_id);

    /////////
    edma_stop(dma_ch1);
  edma_free_channel(dma_ch1);

  edma_stop(dma_ch2);
  edma_free_slot(dma_ch2);
  edma_free_channel(dma_ch2);
  edma_stop(dma_ch3);
  edma_free_slot(dma_ch3);
  edma_free_channel(dma_ch3);

  dma_free_coherent(NULL, BUFFSIZE, bufdest1,physdest1);
  dma_free_coherent(NULL, BUFFSIZE, bufdest2,physdest2);
    ////////

    return 0;
}

static int mcbsp_drv_ioctl(struct inode *inode,struct file *file,unsigned int cmd,unsigned long arg)
{

    int reg_read_pinmux1;
    int i;
    switch(cmd)
    {
    case 1:
      {
       dev->tx_params.word_length1 = word_len;
         dev->rx_params.word_length1 = word_len;

       dev->tx_params.frame_length1 = frame_len;
         dev->rx_params.frame_length1 = frame_len;

       dev->tx_params.word_length2 = word_len;
     dev->rx_params.word_length2 = word_len;

       dev->tx_params.buf_fmt = buf_fmt;
     dev->rx_params.buf_fmt = buf_fmt;

       dev->tx_params.data_delay = data_delay;
     dev->rx_params.data_delay = data_delay;

     davinci_mcbsp_config_params(dev, master);
     dev->tx_params.numevt = numevt;
         dev->rx_params.numevt = numevt;
         davinci_mcbsp_config_multichannel_mode(dev);
         dev->op_mode = DAVINCI_MCBSP_IRQ_MODE;

       //just_do_the_while(); //add

       printk("Starting McBSP RX\n");
       mcbsp_dma_start_rx(dev);
     davinci_mcbsp_start_rx(dev);
      }
      break;
      case 11:
      printk("Yi-Ma-IOCTL-21\n");
      printWelcomeBanner();
      //davinci_mcbsp_stop_rx(dev);
      break;
     case 2:
       printk("\n****** Hello,Kitty - 1 ******\n");
      break;
     case 21:
       printk("\n****** Hello,Kitty - 2 ******\n");
       break;
     default:
      printk("\n****** Hello,Kitty - 3 ******\n");
      return 0;
    }

    return 0;
}

struct file_operations mcbsp_drv_fops =
{
    read:    mcbsp_drv_read,
    write:   mcbsp_drv_write,
    ioctl:   mcbsp_drv_ioctl,
    open:    mcbsp_drv_open,
    release: mcbsp_drv_release,
};

module_init (mcbsp_drv_init);
module_exit (mcbsp_drv_exit);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("QinBinWang-Uijin");
MODULE_DESCRIPTION("MCBSP Driver");

over 14 years ago

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