PKTDMA priority assignment.

Hello,

The Packet DMA Priority Allocation register defines priority for the Packet DMA Secondary master port which is used to access the external linking RAM. 

The Priority Control Register defines priority for the Packet DMA Primary master port which is used for other memory accesses as well as queue push/pop operations destined for the Multicore Navigator slave port.

The Tx Channel N Scheduler Configuration Register found in the TX Scheduler Configuration Region is scheduling priority at the peripheral level among the peripheral's Packet DMA channels. 

The Priority Control Register found in the Global Control Registers Region is scheduling priority at the system level among multiple peripherals.

Regards,

Sahil

Sahil,

1. Does Packet DMA Priority Allocation register should be handled through KICK0/KICK1 mode? Can you please mention me a use case where this Packet DMA priority Allocation register is considered?

2. For AIF module there is no  Tx Channel Scheduler configuration register in this case how do we set PKTDMA_PRI for AIF?

regards,

YCS

1. As part of the boot configuration region, the Packet DMA Priority Allocation register should in fact be handled through the kicker mechanism. This register should be used when access to external linking RAM requires higher priority than other masters going through the main SCR.

2. For AIF you are correct, there is no TX Channel Scheduler configuration register. AIF's scheduler allows for scheduling between DIO data and Packet DMA data, but there is no option to prioritize the individual Packet DMA channels within AIF.

Regards,

Sahil

Thanks for the reply.

Sahil,

If I have to use CPPI & QMSS LLD for AIF2 in that case how to configure the Rx flow configuration register i.e  Cppi_RxFlowCfg.flowIDNum ?.

I couldn't able to figure it out how to use CPPI LLD to  configure  AIF2 specific parameters in to the AIF2 PKTDMA FLOW REGION(i.e 0x1F1A000  memory map for AIF2 Rx flow region). I am not sure whether it is referenced via CPPI handle which is created for AIF and passed to CPPI API 

Hello,

If you are using the CPPI LLD for AIF2 RX flow configuration, the flow parameters are part of the Cppi_RxFlowCFg parameter you have listed above. You can find this data structure in the cppi_drv.h file and it includes fields such as flowIdNum.

Regards,

Sahil

Hi,

I was able to find out the mechanism to configure the RxFlow for AIF2 and succesfully receivng data from the other DSP(AIF2 testing b/w DSP to DSP). I am facing problem in transmit direction as I am trying push the mono descriptor using CPPI LLD APIs(configured as below for transmit free queue  ) via 512 queue number(i.e AIF2 dedicated queue).I could see desciptor updated as word 0 -> 0x80102280 ,word 1 -> 0x00000000  ,word2 -> 0x000107DE  but it seems AIF2 PKTDMA  is not able to transmit the queue data.Can you please suggest in this regard.

    /* Setup the descriptors for transmit free queue */
    /* Memory region obtained is zero since there is only Qmss_insertMemoryRegion() call.
     * else find the memory region using Qmss_getMemoryRegionCfg() */
    descCfg.memRegion = Qmss_MemRegion_MEMORY_REGION0;
    descCfg.descNum = 1;
    descCfg.destQueueNum = QMSS_PARAM_NOT_SPECIFIED;
    //descCfg.queueType = Qmss_QueueType_STARVATION_COUNTER_QUEUE;
    descCfg.queueType = Qmss_QueueType_GENERAL_PURPOSE_QUEUE;
    descCfg.initDesc = Cppi_InitDesc_INIT_DESCRIPTOR;
    descCfg.descType = Cppi_DescType_MONOLITHIC;
    descCfg.epibPresent = Cppi_EPIB_NO_EPIB_PRESENT;

    descCfg.cfg.mono.dataOffset = 16;
   
    /* Descriptor should be recycled back to Queue Number 1000 */
    descCfg.returnQueue.qMgr = CPPI_COMPLETION_QUE_MGR;
    descCfg.returnQueue.qNum = CPPI_COMPLETION_QUE_NUM;

I could able to figure it out myself.Now i could see test passed from DSP2 to DSP1 but some issue with DSP1 to DSP2 test data Tx .May be issues with qmss & cppi lld library optimization level used.Need to check on it.

regards,

YCS