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TDA4VE-Q1: Power-down sequence

one and zero
Mastermind 18136 points
Part Number: TDA4VE-Q1

Hi Champs,

Reference: TDA4VE datasheet page 124

Q1: Is the Delay between Reset and start of disable of first voltage required or can it be at the same time?

Q2: The datasheet specifies only discharge start times. Due to different amount of decoupling capacitors this may lead to the scenario that a later rail is discharged below 200mV before an earlier rail. Is this acceptable for the TDA4VE/L? Example: +1V8_MCU vs +0V85_MCU or +3V3_SOC vs +1V8_SOC in this picture.

Q3: Would the power-down in this picture satisfy the TDA4 requirements?

Q4: Would it be acceptable to start the discharge of +1V8_SOC already at T2 or even T1? Due to the higher voltage compared to +0V85, +1V1, ... it would always be higher, but the overall shutoff time could be reduced by several ms.

Kind regards, one and zero

  • 0
    TI__Mastermind 18136 points

    Is it possible to make a statement to the questions raised here? Thanks ....

  • 0 in reply to one and zero
    TI__Expert 6965 points

    Q1: The delay btw asserting PORz low and the 1st supply being disabled is intentional.  It allows the reset signal to propagate across the SoC and put all processor domains into reset state before disabling supplies.

    Q2: The power down seq is specifying power supply disable start times (aka "discharge start times") since the key concern is to not continue driving a supply from a low impedance source as other supplies are disabled in approximately the reverse order of the power up seq. The energy left in capacitors can discharge over time without impacting SoC.

    Q3: No, for following reasons:
           1 PORz must be asserted low at least 500us prior to starting power down seq.
           2 DDR 1.1V & SRAM 0.85V supplies must power down 1 step before CORE 0.85V & CPU AVS

    Q4: Goal is to disable supplies in reverse order of power up seq to ensure no "bleed current" paths. With that said, it is recognized that disabling a supply removes "bleed current" paths being driven from higher voltages. However, TI does not validate the many different variants of power sequencing. Only the recommended power up & down sequences are validated. Any other seqs could negatively impact SoC POH reliability.