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SK-TDA4VM: booting MCU2_0 through Linux running on A72

SuryaPrakash Durairaj
Prodigy 230 points
Part Number: SK-TDA4VM

Hi,

I am trying to load IPC example for MCU2_0 core using the Linux running from A72 core. I have customized the memory map for IPC example, increased the DDR size for the MCU2_0 core and tried to load using the linux. I have made all the necessary changes in the k3-j721e-rtos-memory-map.dtsi File, I have increased the CORE memory region size, but still getting the errors , please help me resolve it.

I am getting the following errors

platform 5c00000.r5f: configured R5F for remoteproc mode

 remoteproc remoteproc4: 5c00000.r5f is available

remoteproc remoteproc4: Booting fw image j7-main-r5f0_0-fw, size 530072

remoteproc remoteproc4: bad phdr da 0xa2000000 mem 0x84c00

 remoteproc remoteproc4: Failed to load program segments: -22

Regards,

Surya

  • 0
    TI__Guru* 85266 points

    Hi Surya,

    SuryaPrakash Durairaj said:
    I am trying to load IPC example for MCU2_0 core using the Linux running from A72 core. I have customized the memory map for IPC example, increased the DDR size for the MCU2_0 core and tried to load using the linux. I have made all the necessary changes in the k3-j721e-rtos-memory-map.dtsi File, I have increased the CORE memory region size, but still getting the errors , please help me resolve it

    Could you help me understand the commands used to load the example on MCU2_0?

    Are you using vision_apps here?

    Could you let me know what are the memory related changes done in k3-j721e-rtos-memory-map.dtsi ?

    Regards,

    Nikhil

  • 0 in reply to Nikhil Dasan
    Prodigy 230 points

    Hi,

    I am loading the firmware by doing the following,

    1. Created a folder wtx_app inside /lib/firmware and pasted the MCU2_0 IPC example inside that folder.

    2.  I ran the command ln -s /lib/firmware/wtx-app/ipc_echo_test_mcu2_0_release.xer5f  j7-main-r5f0_0-fw

    I generated a memory map file and device tree file using the python script, after going through the vision apps demo.

    I am attaching the memory map file and the device tree file for you to see.

    The below is the memory map I generated for the MCU2_0 core 

    MEMORY
    {
        /* R5F_TCMA_VECS [ size 64 B ] */
        R5F_TCMA_VECS            (    X ) : ORIGIN = 0x00000000 , LENGTH = 0x00000040
        /* R5F_TCMA [ size 31.94 KB ] */
        R5F_TCMA                 (    X ) : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
        /* Main OCRAM for MCU2_0 [ size 256.00 KB ] */
        MAIN_OCRAM_MCU2_0        ( RWIX ) : ORIGIN = 0x03600000 , LENGTH = 0x00040000
        /* R5F_TCMB0 [ size 32.00 KB ] */
        R5F_TCMB0                ( RWIX ) : ORIGIN = 0x41010000 , LENGTH = 0x00008000
        /* DDR for MCU2_0 for Linux IPC [ size 1024.00 KB ] */
        DDR_MCU2_0_IPC           ( RWIX ) : ORIGIN = 0xA2000000 , LENGTH = 0x00100000
        /* DDR for MCU2_0 for Linux resource table [ size 1024 B ] */
        DDR_MCU2_0_RESOURCE_TABLE ( RWIX ) : ORIGIN = 0xA2100000 , LENGTH = 0x00000400
        /* DDR for MCU2_0 for code/data [ size 31.00 MB ] */
        DDR_MCU2_0               ( RWIX ) : ORIGIN = 0xA2100400 , LENGTH = 0x01EFFC00
        /* Memory for IPC Vring's. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
        IPC_VRING_MEM                     : ORIGIN = 0xAA000000 , LENGTH = 0x02000000
        /* Memory for remote core logging [ size 256.00 KB ] */
        APP_LOG_MEM                       : ORIGIN = 0xAC000000 , LENGTH = 0x00040000
        /* Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent [ size 63.75 MB ] */
        TIOVX_OBJ_DESC_MEM                : ORIGIN = 0xAC040000 , LENGTH = 0x03FC0000
        /* Memory for shared memory buffers in DDR [ size 512.00 MB ] */
        DDR_SHARED_MEM                    : ORIGIN = 0xB8000000 , LENGTH = 0x20000000
        /* DDR for MCU2_0 for local heap [ size 16.00 MB ] */
        DDR_MCU2_0_LOCAL_HEAP    ( RWIX ) : ORIGIN = 0xD9000000 , LENGTH = 0x01000000
        /* Inter-core ethernet shared desc queues. MUST be non-cached or cache-coherent [ size  8.00 MB ] */
        INTERCORE_ETH_DESC_MEM            : ORIGIN = 0xE4000000 , LENGTH = 0x00800000
        /* Inter-core ethernet shared data buffers. MUST be non-cached or cache-coherent [ size 24.00 MB ] */
        INTERCORE_ETH_DATA_MEM            : ORIGIN = 0xE4800000 , LENGTH = 0x01800000
    }
    The below is the changes I made inside the reserved memory node of  k3-j721e-rtos-memory-map.dtsi
    wtx_apps_mcu_r5fss0_core0_dma_memory_region: wtx-apps-r5f-dma-memory@a0000000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xa0000000 0x00 0x00100000>;
    no-map;
    };
    wtx_apps_mcu_r5fss0_core0_memory_region: wtx-apps-r5f-memory@a0100000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xa0100000 0x00 0x00f00000>;
    no-map;
    };
    wtx_apps_mcu_r5fss0_core1_dma_memory_region: wtx-apps-r5f-dma-memory@a1000000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xa1000000 0x00 0x00100000>;
    no-map;
    };
    wtx_apps_mcu_r5fss0_core1_memory_region: wtx-apps-r5f-memory@a1100000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xa1100000 0x00 0x00f00000>;
    no-map;
    };
    wtx_apps_main_r5fss0_core0_dma_memory_region: wtx-apps-r5f-dma-memory@a2000000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xa2000000 0x00 0x00100000>;
    no-map;
    };
    wtx_apps_main_r5fss0_core0_memory_region: wtx-apps-r5f-memory@a2100000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xa2100000 0x00 0x07f00000>;
    no-map;
    };
    wtx_apps_main_r5fss0_core1_dma_memory_region: wtx-apps-r5f-dma-memory@aa000000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xaa000000 0x00 0x00100000>;
    no-map;
    };
    wtx_apps_main_r5fss0_core1_memory_region: wtx-apps-r5f-memory@aa100000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xaa100000 0x00 0x00f00000>;
    no-map;
    };
    wtx_apps_main_r5fss1_core0_dma_memory_region: wtx-apps-r5f-dma-memory@ab000000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xab000000 0x00 0x00100000>;
    no-map;
    };
    wtx_apps_main_r5fss1_core0_memory_region: wtx-apps-r5f-memory@ab100000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xab100000 0x00 0x00f00000>;
    no-map;
    };
    wtx_apps_main_r5fss1_core1_dma_memory_region: wtx-apps-r5f-dma-memory@ac000000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xac000000 0x00 0x00100000>;
    no-map;
    };
    wtx_apps_main_r5fss1_core1_memory_region: wtx-apps-r5f-memory@ac100000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xac100000 0x00 0x00f00000>;
    no-map;
    };
    wtx_apps_c66_1_dma_memory_region: wtx-apps-c66-dma-memory@ad000000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xad000000 0x00 0x00100000>;
    no-map;
    };
    wtx_apps_c66_0_memory_region: wtx-apps-c66-memory@ad100000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xad100000 0x00 0x00f00000>;
    no-map;
    };
    wtx_apps_c66_0_dma_memory_region: wtx-apps-c66-dma-memory@ae000000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xae000000 0x00 0x00100000>;
    no-map;
    };
    wtx_apps_c66_1_memory_region: wtx-apps-c66-memory@ae100000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xae100000 0x00 0x00f00000>;
    no-map;
    };
    wtx_apps_rtos_ipc_memory_region: wtx-apps-rtos-ipc-memory-region {
    reg = <0x00 0xaf000000 0x00 0x02000000>;
    alignment = <0x1000>;
    no-map;
    };
    wtx_apps_c71_0_dma_memory_region: wtx-apps-c71-dma-memory@b1000000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xb1000000 0x00 0x00100000>;
    no-map;
    };
    wtx_apps_c71_0_memory_region: wtx-apps-c71-memory@b1100000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xb1100000 0x00 0x05f00000>;
    no-map;
    };
    wtx_apps_core_heaps_lo: wtx-apps-core-heap-memory-lo@b7000000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xb7000000 0x00 0x0c000000>;
    no-map;
    };
    wtx_apps_main_r5fss0_core0_shared_memory_queue_region: wtx-apps-r5f-virtual-eth-queues@c3000000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xc3000000 0x00 0x00800000>;
    no-map;
    };
    wtx_apps_main_r5fss0_core0_shared_memory_bufpool_region: wtx-apps-r5f-virtual-eth-buffers@c3800000 {
    compatible = "shared-dma-pool";
    reg = <0x00 0xc3800000 0x00 0x01800000>;
    no-map;
    };
    wtx_apps_core_heaps_hi: wtx-apps-core-heap-memory-hi@880000000 {
    compatible = "shared-dma-pool";
    reg = <0x08 0x80000000 0x00 0x27000000>;
    no-map;
    };
  • 0 in reply to SuryaPrakash Durairaj
    TI__Guru* 85266 points

    Hi Surya,

    Thank you for sharing the information.

    But here, may I know what is change that you have done? I see that the VRING address and the MCu2_0 code region still have the same base address and size as of vision_apps in the SDK.

    SuryaPrakash Durairaj said:
    I am trying to load IPC example for MCU2_0 core using the Linux running from A72 core. I have customized the memory map for IPC example, increased the DDR size for the MCU2_0 core and tried to load using the linux

    Could you please let me know where the above-mentioned change is?

    Also, are you able to run the IPC example without memory map customization?

    Regards,

    Nikhil

  • 0 in reply to Nikhil Dasan
    Prodigy 230 points

    Hi Nikhil,

    Vision Apps Example:

        /* DDR for MCU2_0 for code/data [ size 31.00 MB ] */
        DDR_MCU2_0               ( RWIX ) : ORIGIN = 0xA2100400 , LENGTH = 0x01EFFC00
    Customized memory change:
        /* DDR for MCU2_0 for code/data [ size 127.00 MB ] */
        DDR_MCU2_0               ( RWIX ) : ORIGIN = 0xA2100400 , LENGTH = 0x07EFFC00
    If you observe the above line, I have increased the size of DDR_MCU2_0 to 127MB, in the vision apps example it was only 31MB, this is the major change in my customization.
    With respect to the IPC example, I have tried the IPC example without any memory customization, and it was working without any issue. Only when I change the size, it is not working that's what I observed.
    Regards,
    Surya
  • 0 in reply to SuryaPrakash Durairaj
    TI__Guru* 85266 points

    Hi,

    SuryaPrakash Durairaj said:
    /* DDR for MCU2_0 for Linux resource table [ size 1024 B ] */
        DDR_MCU2_0_RESOURCE_TABLE ( RWIX ) : ORIGIN = 0xA2100000 , LENGTH = 0x00000400
        /* DDR for MCU2_0 for code/data [ size 31.00 MB ] */
        DDR_MCU2_0               ( RWIX ) : ORIGIN = 0xA2100400 , LENGTH = 0x01EFFC00
        /* Memory for IPC Vring's. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
        IPC_VRING_MEM                     : ORIGIN = 0xAA000000 , LENGTH = 0x02000000
        /* Memory for remote core logging [ size 256.00 KB ] */
        APP_LOG_MEM                       : ORIGIN = 0xAC000000 , LENGTH = 0x00040000

    So, you have increased the code region of MCU2_0 from 31MB to 127 MB. May I know why have you increased this region?

    In the linker file attached above, your IPC_VRING_MEM still has 0xAA000000 as the base address whereas in the linux file it is different.
    You should make the same changes here too.

    Could you let me know if you are running IPC only on MCU2_0 or are the other cores (MCU2_1, C66, C7 etc) involved as well?

    Regards,

    Nikhil

  • 0 in reply to Nikhil Dasan
    Prodigy 230 points

    Hi Nikhil,

    Sorry I have shared the vision example file previously, 

    Here is the customized memory map file created by me

    MEMORY
    {
        /* R5F_TCMA_VECS [ size 64 B ] */
        R5F_TCMA_VECS            (    X ) : ORIGIN = 0x00000000 , LENGTH = 0x00000040
        /* R5F_TCMA [ size 31.94 KB ] */
        R5F_TCMA                 (    X ) : ORIGIN = 0x00000040 , LENGTH = 0x00007FC0
        /* Main OCRAM for MCU2_0 [ size 256.00 KB ] */
        MAIN_OCRAM_MCU2_0        ( RWIX ) : ORIGIN = 0x03600000 , LENGTH = 0x00040000
        /* R5F_TCMB0 [ size 32.00 KB ] */
        R5F_TCMB0                ( RWIX ) : ORIGIN = 0x41010000 , LENGTH = 0x00008000
        /* DDR for MCU2_0 for Linux IPC [ size 1024.00 KB ] */
        DDR_MCU2_0_IPC           ( RWIX ) : ORIGIN = 0xA2000000 , LENGTH = 0x00100000
        /* DDR for MCU2_0 for Linux resource table [ size 1024 B ] */
        DDR_MCU2_0_RESOURCE_TABLE ( RWIX ) : ORIGIN = 0xA2100000 , LENGTH = 0x00000400
        /* DDR for MCU2_0 for code/data [ size 127.00 MB ] */
        DDR_MCU2_0               ( RWIX ) : ORIGIN = 0xA2100400 , LENGTH = 0x07EFFC00
        /* Memory for IPC Vring's. MUST be non-cached or cache-coherent [ size 32.00 MB ] */
        IPC_VRING_MEM                     : ORIGIN = 0xAF000000 , LENGTH = 0x02000000
        /* DDR for MCU2_0 for local heap [ size 16.00 MB ] */
        DDR_MCU2_0_LOCAL_HEAP    ( RWIX ) : ORIGIN = 0xB8000000 , LENGTH = 0x01000000
        /* Inter-core ethernet shared desc queues. MUST be non-cached or cache-coherent [ size  8.00 MB ] */
        INTERCORE_ETH_DESC_MEM            : ORIGIN = 0xC3000000 , LENGTH = 0x00800000
        /* Inter-core ethernet shared data buffers. MUST be non-cached or cache-coherent [ size 24.00 MB ] */
        INTERCORE_ETH_DATA_MEM            : ORIGIN = 0xC3800000 , LENGTH = 0x01800000
    }
    I have increased the code region, because my application size was bigger, when I compiled with default memory map, I got error from the compiler stating that my application size is large, so I have increased the code memory.
    Currently I am running only the MCU2_0 core alone , not running C66 and C7 cores.
  • 0 in reply to SuryaPrakash Durairaj
    TI__Guru* 85266 points

    Hi,

    In this case, it looks correct.
    Is your ipc example based on the ipc echo test from the PDK example?

    if yes, could you please double confirm if the VRING_BASE_ADDRESS that is being passed to the Virtio IPC module initialization is also 0xAF000000?
    Because, in pdk based examples, i see this base address being hard-coded.

    Regards,

    Nikhil