OMAP4430 Dual Rank DDR

Hello,

An update to our question above:

The TI OMAP4430 TRM (swpu231ap.pdf) states that the ZQ Cal can be setup to be performed serially between CS0 and CS1 of the DDR memory. We currently are using the SFEXITEN option and are NOT using the DUALCALEN registers. (So this should be setup for CS0 & CS1 to be performed serially/*per chip-select*)

In our case we have switched to a dual channel dual rank part so there are 4 chip selects. CS0P0, CS0P1, CS1P0, and CS1P1. In order to ensure there are no issues with the new memory we need to confirm how the OMAP handles the ZQ Cal.

Do you know what order of chip selects it performs the ZQ Cal on? We want to make sure we don’t have a loading problem with our RZQ setup.

Ideally both CS0 ranks on each channel are performed and then both CS1 ranks on each channel

Kara, i don't think the ZQ cal can be performed on each channel separately, but the serial calibration would be performed on CS0 first, then CS1.

Are you using both EMIFs and connecting the 2 CS on each EMIF?  

Regards,

James

Hi James, Thank your for for the response.

We have More questions/Comments:

                We are okay if both channels ZQ cal at the same time so long as they don’t ZQ cal each rank at the same time for each channel. We don’t want to parallel ZQ Cal both Ranks on the same channel simultaneously because each channel shares the RZQ across the 2 ranks.

                Would you agree that the OMAP performs the ZQ cal similar to the attached images for the CS0/CS1 chip-selects. Channel a & b are performed at the same time (2 x EMIFs) and first the CS0’s on both channels are performed then both CS1’s.

                We would like to use a Dual Rank Dual Channel POP DDR, this parts would connect all 4 chip-selects to the OMAP so connections to both EMIFs will be made. (although I’m not 100% sure we’re using the second EMIF)

                We are looking for confirmation from TI that the OMAP can properly handle the ZQ Cal for dual rank dual channel memories

Hi Brad,

I think you have some flexibility on how the zq cal is perform.  First, since there are 2 EMIFs, each with a separate register set, you can control the sequencing of the zq cal for each of these.  And with the registers mentioned above, the zq cal for each CS can be sequenced within each EMIF

Can you still confirm how the memories are connected?  I think you could connect 1 EMIF to two CS, each CS controls 2 channels, or you could connect 2 EMIFs (4 CS), and each CS controls one channel. I think either way, you can separate the zq cal for channel A vs channel B.

Regards,

James   

Thank you James! Response back to the questions below:

                We are using the EMIF1 and EMIF2 in 128-byte interleaved mode and the EMIF config is then applied to both EMIF1 and EMIF2. We were using a single channel single rank part previously, so 2 chip selects, and have now swapped in a larger capacity dual channel dual rank part and want to make sure that there isn’t any issues with the ZQ Cal of the dual rank dual channel part if it’s left in this configuration. We’re only ½ of the new dual channel dual rank part but left the config the same and want to ensure there won’t be any ZQ Cal issues across the ranks.

Again we have the DUALCALEN disabled, Do you know if this may cause issues with trying to ZQ Cal the 2 ranks simultaneously on each channel?

We are okay if Channel A and Channel B execute simultaneously just as long as both ranks don’t per channel, so for each channel CS0_a & CS1_a ZQ Cal cannot occur at the same time. CS0_a and CS0_b can occur at the same time likewise as to CS1_a and CS1_b. (Similar to the pictures I’ve previously shared)