AM6442: GPMC use as peripheral bus

Genius 3186 points

Part Number: AM6442

May I have some questions about GPMC?

My customer want to use GPMC as perpheral bus to connect ASIC.

Use as 16-bit bus, Async, non-multiplexed.

Question1

The ASIC not need CLK, WPn, ADVn_ALE, CSn[1-3].

Could we use without these pins?

Question2

In data reading code, we can see the data tranmit in logicanalyser.

But GPMC_PREFETCH_STATUS.COUNTVALUE can not count down.

Could you tell me anything wrong setting if you think.

Question3

The fiched data will locate GPMC0_DATA(0x050000000 - 0x057FFFFFF)?

we could read fitched data as direct access 0x050000000 in user space?

Question4

If there is anything docment/ information about GPMC use as peripheral bus,

Could you let me?

settings

GPMC_CONFIG1 (0x3B00 0060) = 0x00001001;

GPMC_CONFIG7 (0x3B00 0078) = 0x00000F40;

another register will not changed in init section.

Thanks,

over 3 years ago

0 Swargam Anil over 3 years ago

TI__Guru 54828 points

Hello GR,

I am working on your thread.

You may get a reply in one or two days.

Regards,

S.Anil.

0 GR over 3 years ago in reply to Swargam Anil

Genius 3186 points

Hello Anil,

Thanks to your supporting.

Is there any information or update?
Best regards,

0 Swargam Anil over 3 years ago in reply to GR

TI__Guru 54828 points

Hello GR,

I can provide a reply by EOD.

Sorry for the delayed response, as I was fixing other escalations.

Regards,

S.Anil.

0 Swargam Anil over 3 years ago in reply to Swargam Anil

TI__Guru 54828 points

Hello GR,

GR said:
The ASIC not need CLK, WPn, ADVn_ALE, CSn[1-3].

Could we use without these pins?

As per your comments, you are interfacing GPMC to the ASIC in Asynch mode.

then you don't need a CLOCK signal.

I am assuming that you are reading address space within the 256 MB, so you don't need other chip selection pins and need only one chip selection.

The WP signal is used to protect the device from accidental programming or erasing, and it should only be used in Memory interface applications, but in your use case, it is not required.

GR said:
Question2

In data reading code, we can see the data tranmit in logicanalyser.

But GPMC_PREFETCH_STATUS.COUNTVALUE can not count down.

Could you tell me anything wrong setting if you think.

--

Question3

The fiched data will locate GPMC0_DATA(0x050000000 - 0x057FFFFFF)?

we could read fitched data as direct access 0x050000000 in user space?

Can you please confirm you are interfacing GPMC to either R5F or A53?

Since the above code is not available in RTOS, it looks like you are interfacing with the A53 core.

Regards,

S.Anil.

0 GR over 2 years ago in reply to Swargam Anil

Genius 3186 points

Hello Anil,

Thanks to your information.

Swargam Anil said:
As per your comments, you are interfacing GPMC to the ASIC in Asynch mode.

then you don't need a CLOCK signal.

I am assuming that you are reading address space within the 256 MB, so you don't need other chip selection pins and need only one chip selection.

The WP signal is used to protect the device from accidental programming or erasing, and it should only be used in Memory interface applications, but in your use case, it is not required.

I understand.

It seem we could use GPMC as peripheral bus connect to my customer's ASIC.

Swargam Anil said:
Can you please confirm you are interfacing GPMC to either R5F or A53?

Since the above code is not available in RTOS, it looks like you are interfacing with the A53 core.

My customer is interfacing with R5F core.

And coding in bare-metal with reference to TRM.

If access main domain memory address from R5F, we need to use RAT module regardless of 32bit or less or more?

May I have one more question?

We could read the fetched data from memory address in GPMC_NAND_DATA(0x3B00 0084) ?

Or the fetched data will locate GPMC0_DATA(0x050000000 - 0x057FFFFFF)?

I would to know how to read fetched data.

Best regards,

0 Swargam Anil over 2 years ago in reply to GR

TI__Guru 54828 points

Hello GR,

I am in training, and you may get a reply by EOD.

Regards,

S.Anil.

+1 Swargam Anil over 2 years ago in reply to GR

TI__Guru 54828 points

GR,

GR said:
My customer is interfacing with R5F core.

And coding in bare-metal with reference to TRM.

If access main domain memory address from R5F, we need to use RAT module regardless of 32bit or less or more?

R5F can directly access all SOC memories, and most of the time, RAT is not needed in the R5F application.

If you are trying to access more than 32-bit address space on the R5F core, then you need the RAT configuration.

GR said:
May I have one more question?

We could read the fetched data from memory address in GPMC_NAND_DATA(0x3B00 0084) ?

Or the fetched data will locate GPMC0_DATA(0x050000000 - 0x057FFFFFF)?

I would to know how to read fetched data.

Please see the below snippet, taken from AM62X.

FYI, the GPMC example is already available for AM62X users.

You can look at the GPMC driver and try to implement the same thing for AM64X since both are K3 architectures and almost all IPs are the same.

To answer your question, the data should be reading the chipset base address.

/* Perform CPU read with prefetch read engine. */

/* Enable prefetch read engine. */
status += GPMC_prefetchPostWriteConfigEnable(handle, GPMC_PREFETCH_ACCESSMODE_READ, byteCount, FALSE);

if(status == SystemP_SUCCESS)
{
uint32_t *ptr = (uint32_t *)trans->Buf;

while(byteCount)
{
/* Get GPMC FIFO counter value. */
threshold = CSL_REG32_FEXT(attrs->gpmcBaseAddr + CSL_GPMC_PREFETCH_STATUS, GPMC_PREFETCH_STATUS_FIFOPOINTER);

for(uint32_t i =0; i< threshold/4;i++)
{
*ptr++ = *(volatile uint32_t*)attrs->chipSelBaseAddr;
byteCount -=4;
}

Regards,

S.Anil.

Processors

Processors forum

AM6442: GPMC use as peripheral bus