TMS320C6657: TMS320C6657: Enable DDR3 ECC in C6657 platform causes random errors

Tam tran,

I believe the "initFlag.ecc" code belongs to the platform test - Sample code of Processor SDK 6.3.

This platform test code doesnot exist in MCSDK_2_01_02_06. 

Either you have to use the latest processor SDK 6.3 (or) integrate this code to MCSDK_2_01_02_06.

Regards

Shankari G

Hi Shakari

My bad, it was a typo error.

Let's me ask the question again: we are using pdk_C6657_1_1_2_6\packages\ti\platform\evmc6657l\platform_lib

Some of the example e.g.

- the file "bench_srio.c" where the ECC is disable

FormFlags.pll = 0; /* PLLs for clocking */
pFormFlags.ddr = 0; /* External memory */
pFormFlags.tcsl = 1; /* Time stamp counter */
pFormFlags.phy = 0; /* Ethernet */
pFormFlags.ecc = 0; /* Memory ECC */ <-- ECC is disable

pFormConfig.pllm = 0; /* Use libraries default clock divisor */
pFormStatus = platform_init(&pFormFlags, &pFormConfig);

- "platform_test.c"

memset(&args, 0x01, sizeof(test_config));
memset(&init_flags, 0x01, sizeof(platform_init_flags)); <-- ECC is enable here
...

if (platform_init(&init_flags, &init_config) != Platform_EOK) {
printf("Platform failed to initialize, errno = 0x%x \n", platform_errno);

How did you test if the ECC is working or not in your test code?

In our SW if the ECC is enable (with only setting this ECC bit and call platform_init) then some time loading code to the DDR3 fails when we'll try to launch.

Disable the ECC then our sw launch stable. 

So my question is: is it the only action we should do if we'll need to enable ECC (set the only bit before calling paltform_init) or do we need to configure other part of configuration in SW

BR

Tam Tran 

Tam tran,

platform test is just a sample example for reference....

For enabling and disabling the DDR3-ECC, we have to rely on the datasheet and the sections on DDR3 and ECC.

Regards

Shankari G

Hi Shankari

Sorry that i need to re-open the question again.

From sprugv8e section 2.17:

Question 1:

>>>>>>>>>>>> 

The ECC is stored inside the SDRAM during writes. After enabling ECC and before
performing any functional reads or writes, all DDR3 memory space configured as ECC
should be first written with known data that is 64-bit aligned and multiples of 64-bit. This is to
ensure the correct ECC values are stored in the ECC SDRAM prior to functional use.

<<<<<<<<<<<<<

"first written with known data": is 0 is Ok as known data or should it be some other pattern?

Question 2:

>>>>>>>>>>>

A write access with byte count that is not a multiple of 64-bit quanta, or with a non-64-bit-aligned address
performed within the address range protected by ECC, will result in a write ECC error interrupt. In this
case, the DDR3 memory controller writes to the SDRAM. However, the ECC value written to the SDRAM
will be corrupted

<<<<<<<<<<<<<<

Is there any option for alignment of 64-bit we can set in the linker? It's a nightmare if we have to go through all our code to manually set DATA_ALIGN of 64-bit for every variables located in DDR3.

Question 3:

>>>>>>>>>>>>>>>>>>>>

If there is a one-bit error, the DDR3 memory controller corrects the data and sends it on the read
interface. For 2-bit errors, the DDR3 memory controller generates a read ECC error interrupt. Note that in
both cases, the data in SDRAM is still corrupted. It is the responsibility of system software to go and
correct the data in the SDRAM

<<<<<<<<<<<<<<<<<<<

What do you mean with the responsibility of the "system software" in case of one-bit error and 2-bit error: the SDRAM is still corrupted and which part of teh sw should be in chared to correct the data in the SDRAM?

Question 4:

 >>>>>>>>>>>>>>

If ECC is disabled, the ECC byte lane is held in reset to save power. Hence, full-leveling
must be triggered after enabling ECC to ensure that the ECC byte lane is leveled

<<<<<<<<<<<<<<<<<<<<<<

The statement means the setup of levelling MUST be done AFTER the ECC is enable. Is there any specific lanes of ECC the staement is referred to ?

BR

Tam

Tam,

Please open up a new query.

Regards

Shankari G