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TMS320C6727B : EMIF bus utilisation with three devices connected

Ashwin5763
Prodigy 70 points
Other Parts Discussed in Thread: TMS320C6727B

Hello,


We are using the deivce TMS320C6727B. As per design, three devices connected onto the same EMIF Bus viz. Flash(16-bit), FPGA(16-bit), SDRAM(32-bit).

Following are the two transfers on EMIF Bus,
1) Application will be residing in the Flash and at Boot-up it needs to be transferred to SDRAM. And the code execution will be done from SDRAM. So the program access will be done by the CPU. This will use the bridge BR3 of the crossbar switch.
2) Application needs to periodically transfer data from FPGA to SDRAM. This will be a two-stage transfer i.e. from FPGA data will be transferred to DSP internal memory and then from internal memory to SDRAM. This will use the bridge BR4 of the crossbar switch.

The EMIF Bus being common in both the transfers, will it cause any problems. We would like to know how that is there any bus arbitration that can help when these two transfers occur simultaneously as both the devices are connected onto same EMIF bus.

Is any similar implmentation being done earlier by anyone?

Regards,
Ashwin.

  • 0
    TI__Mastermind 18130 points

    Ashwin said:
    The EMIF Bus being common in both the transfers, will it cause any problems.


    There should not be any inherent problems in transferring between two external parts on the EMIF bus. I would like to know how you have connected these three devices as there are only two Chip Selects on the C672x. I realize that the Flash is connected to CS2 and the SDRAM to CS0, but which Chip Select does the FPGA utilize?

    If using the dMAX to copy data from Flash or FPGA into L2, then from L2 to SDRAM there should be minimal issues. Note that if you are caching the contents of external memory that you may need to occasionally Invalidate and/or write-back to ensure that you are always working with current data.


    Ashwin said:
    We would like to know how that is there any bus arbitration that can help when these two transfers occur simultaneously as both the devices are connected onto same EMIF bus.

    The EMIF does not have any built-in logic to allow multiple devices to connect directly on the same Chip Select. If the FPGA and SDRAM utilize the same Chip Select, data will need to be buffered in internal memory and then sent back out in 2 stages as you have outlined above.

    For transfers from CS2 to CS0 (Flash to SDRAM) the dMAX can be used to automatically copy from one CS to the next without buffering the memory internally.

  • 0 in reply to TimHarron
    Prodigy 70 points

     

    Our scheme is to connect both Flash and FPGA on the ASYNC 16-bit interface with chip select CS2. SDRAM is connected on 32-bit SYNC interface on EMIF bus with chip select CS0.

    Flash memory will be required only during the start, till the application program from Flash is copied to SDRAM. This process will happen only during Boot-up. After this FPGA will come into picture on the chip select-CS2. We have used one address line A20 to distinguish the access between FPGA anbd FLASH. During application execution, the data from FPGA needs to be transferred to SDRAM. Hence during Boot-up FLASH will be selected and during run-time, FPGA will be selected.

    Currently we are trying to manage the data to be transfered from FPGA to SDRAM in the DSP internal 256k unified Program/data RAM itself. If the data fits in less than 256k then there is no need to transfer data from FPGA to SDRAM.

    Hope this gives a fair idea about the system.

    Regards,
    Ashwin.

  • 0 in reply to Ashwin5763
    TI__Mastermind 18130 points

    Yes, this helps paint a better picture.

    With your setup I do not see any significant problems that you will run into. The copies between FPGA and SDRAM will probably not be extremely fast, but if your system can handle the transfer delays there should not be any other side effects I can see to deal with.