TDA4VM-Q1: DDR Register Configuration Review

Hi,

An said:

1.We use DDRSS Reg Config Tool 0.6.0 previously, which is updated to 0.10.0 version currently. Then I use the same input information and find there are differences for the generated codes. Could you clarify what points are updated. Are there some change notes?

Yes, there is a revision tab inside the workbook. Any change that is for a particular SOC part number will be listed as such. Otherwise, the change should be global and apply to all part numbers supported by the tool.

An said:

2.Is it related to SDK version for DDRSS Reg Config Tool version. We use SDK7.3 and SDK8.5 for 2 varients of our projects and we use DDRSS Reg Config Tool 0.6.0 for both. Do you recommand updating it to 0.10.0 version?

Please see the E2E below. It is always recommended to use the latest version of the tool. Newer versions of the tool should still be compatible with older versions of the SDK. However, the inverse may not be true. (new versions of the SDK are compatible with older versions of the tool)

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1030581/tda4vm-ddrss-register-configuration-tool-v0-6-0-compatibility-with-prior-sdks-before-8-0 

An said:

3.We did encounter an issue about DDR. So I have to ask for your help. We find DDR stress failed on some test items sometimes, such as Bit spread and bit flip as the below log shows. Additionally, we use TI stress script and find no issues, while find issues with memtester tests. Is this because there are fewer test items in the TI script?

I am not familiar with the TI stress script you have referenced. Though, if the failure is test pattern dependent and the TI stress script does not use the same test pattern used by memtester, than that is likely why one test passes and the other fails.

An said:

4.We just see this failure on 3 boards while we have built thousands of boards. Do you have any advice for this failure mode? Is there any related DDR Reg configuration we can optimize? For this reason, I attach our SCH, DDR Reg Configuration based 0.6.0 version for your review. We use micron DDR MT53E1G32D2FW-046 AUT:B, which is similar with EVM board.

As a first step, I would recommend checking these same boards with the latest version of the register configuration tool. If the issue still persists, I would recommend trying to reduce the DDR frequency to observe the impact. 

Regards,
Kevin

Hello Kevin，

A few questions from me.

Q1 for the new tool, 0.10.0 version.

I see there are DDRSS0,1,2,3 modules and Data Lane 0,1,2,3 in the 0.10.0 version new tool. As we use TDA4VM chips. So do we just need to configurate DDRSS0 and Data Lane 0? How to deal with the others? Just don't care about them, or fill null values，or other values to them？

Q2: In fact, we have 2 varient ECUs for 2 projects. One use SDK7.3. And the other use SDK8.5, which may be updated to SDK9.0 in future.So I would like to know if there are some patch about DDR configuration and training algorithms for SDK 7.3 and SDK8.5, especially for SDK7.3.

We have ever got OSPI issues and fix it by using a patch which update the tuning algorithms. That's why I raise this question and confirm with you.

Thank you in advance.