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J721EXSOMXEVM: Enable all the ethernet ports and can channel on the gateway board.

Abdul Rehman
Prodigy 130 points
Part Number: J721EXSOMXEVM
Other Parts Discussed in Thread: TDA4VM

Hi,

I am facing an issue in accessing all the ethernet ports and CAN channels on the Jacinto7 EVM Gateway/Ethernet Switch Expansion.


I have loaded the ethernet firmware manually and also vision apps.

Following are the things that I have already tried. https://e2e.ti.com/support/processors-group/processors/f/processors-forum/929577/faq-tda4vm-how-to-get-cpsw9g-virtual-interface-functional-on-tda4x-dra8x-sdk-versions-7-0-onward
Vision apps installation: https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/08_06_01_03/exports/docs/vision_apps/docs/user_guide/RUN_INSTRUCTIONS.html.

On this website it is mentioned that there is no need to load ethfw manually. https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/08_06_01_03/exports/docs/vision_apps/docs/user_guide/ETHFW_DEMOS.html

Anyways I have still load ethfw manually by fallowing this software-dl.ti.com/.../ethfw_c_ug_top.html All the 8 ports are alive however, I can't see their MAC.

Moreover, I also want to enable all the CAN channels available on gateway.

 

  • 0
    TI__Guru 64610 points

    Hi,

    Abdul Rehman said:
    I have loaded the ethernet firmware manually and also vision apps.

    If no need to manually load ethernet firmware in case of vision apps.
    Once you prepare SPL boot flow setup, visions apps scripts will map MCU2_0 binary (ethfw + vision apps)  to Main R5F core 0.

    If you are loading server image from ethfw folder then it will be ethfw alone, does not integrate vision applications into it.

    If you are loading mcu2_0 image from visions_apps then it will be with ethfw and vision applications.

    If you follow steps-1, 3 then it will only map firmware image to R5F core.
    https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/vision_apps/docs/user_guide/RUN_INSTRUCTIONS.html#run_steps_linux 

    Abdul Rehman said:
    All the 8 ports are alive however, I can't see their MAC.

    Default EthFw application will enable 2 MAC only Ports and rest all are under switch ports, and it will create one virtual switch interface (eth1) and virtual MAC port interface (eth2) on A72 Linux.
    From eth1 you can send broadcast data from all switch ports, and from eth2 you can send data from Port-1 (default MAC only port mapped to A72).

    From your logs screen, Ethernet application result is correct as per configuration.

    Please refer to EthFw user-guide for more details.

    Abdul Rehman said:
    CAN channels on the Jacinto7 EVM Gateway/Ethernet Switch Expansion

    SDK doesn't have CAN application integrated to Vision Apps.
    We have CAN examples in PDK from "<RTOS_SDK>/<pdk_xx>packages/ti/csl/example/mcan/mcanEvmLoopback" you can use those and test CAN channels.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 130 points

    Here I can only see 4 CAN channels however, in total there are 10 CAN channels. 4 on the main board and 6 on the gateway. How can I enable gateway CAN channels?


    root@j7-evm:~# ifconfig -a
    can0: flags=128<NOARP> mtu 16 metric 1
    unspec 00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00 txqueuelen 10 )
    RX packets 0 bytes 0 (0.0 B)
    RX errors 0 dropped 0 overruns 0 frame 0
    TX packets 0 bytes 0 (0.0 B)
    TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
    device interrupt 23

    can1: flags=128<NOARP> mtu 16 metric 1
    unspec 00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00 txqueuelen 10 )
    RX packets 0 bytes 0 (0.0 B)
    RX errors 0 dropped 0 overruns 0 frame 0
    TX packets 0 bytes 0 (0.0 B)
    TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
    device interrupt 48

    can2: flags=128<NOARP> mtu 16 metric 1
    unspec 00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00 txqueuelen 10 )
    RX packets 0 bytes 0 (0.0 B)
    RX errors 0 dropped 0 overruns 0 frame 0
    TX packets 0 bytes 0 (0.0 B)
    TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
    device interrupt 25

    can3: flags=128<NOARP> mtu 16 metric 1
    unspec 00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00 txqueuelen 10 )
    RX packets 0 bytes 0 (0.0 B)
    RX errors 0 dropped 0 overruns 0 frame 0
    TX packets 0 bytes 0 (0.0 B)
    TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0
    device interrupt 50

    eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500 metric 1
    inet6 fe80::3608:e1ff:fe5b:664d prefixlen 64 scopeid 0x20<link>
    ether 34:08:e1:5b:66:4d txqueuelen 1000 (Ethernet)
    RX packets 19 bytes 5291 (5.1 KiB)
    RX errors 0 dropped 0 overruns 0 frame 0
    TX packets 28 bytes 4860 (4.7 KiB)
    TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

    eth1: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500 metric 1
    inet6 fe80::72ff:76ff:fe1d:92c1 prefixlen 64 scopeid 0x20<link>
    ether 70:ff:76:1d:92:c1 txqueuelen 1000 (Ethernet)
    RX packets 44 bytes 6434 (6.2 KiB)
    RX errors 0 dropped 0 overruns 0 frame 0
    TX packets 27 bytes 4342 (4.2 KiB)
    TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

    eth2: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500 metric 1
    inet6 fe80::72ff:76ff:fe1d:92c2 prefixlen 64 scopeid 0x20<link>
    ether 70:ff:76:1d:92:c2 txqueuelen 1000 (Ethernet)
    RX packets 39 bytes 8257 (8.0 KiB)
    RX errors 0 dropped 0 overruns 0 frame 0
    TX packets 26 bytes 4184 (4.0 KiB)
    TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0

  • 0 in reply to Abdul Rehman
    TI__Guru 64610 points

    Hi,

    Abdul Rehman said:
    Here I can only see 4 CAN channels however, in total there are 10 CAN channels. 4 on the main board and 6 on the gateway

    By default only 4 CAN channels (2 MCU domain and 2 main domain) were enabled in device tress which are in common processor board (Main board).

    Abdul Rehman said:
    How can I enable gateway CAN channels?

    You have to update the device tress such that enable required CAN channels and Pin Mux for those, and enable transceiver corresponding to CAN channels.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 130 points

    Hi Sudheer,

    How can I update the device tree? Can you provide a sample? Also I want to enable all the ethernet ports as MAC ports so I can transfer the data externally through them.

    Best Regards
    Abdul Rehman

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 130 points

    Hi Sudheer,

    Do I need to write the device tree by myself for all the CAN channels? I want to access it from RTOS.
    How can I update the device tree? Can you provide a sample? Also I want to enable all the ethernet ports as MAC ports so I can transfer the data externally through them.

    Best Regards
    Abdul Rehman

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 130 points

    Hi Sudheer,

    I found this information from the documentation.

    How can I set to low. This will activate mux.





  • 0 in reply to Abdul Rehman
    TI__Guru 64610 points

    Hi,

    Abdul Rehman said:
    How can I update the device tree? Can you provide a sample?

    Please refer to the below code/images for enabling GESI CAN ports in Linux from device tress file. (k3-j721e-common-proc-board.dts file to be updated with below info).

    1. Add pin hog for selection of CAN pins from MUX.


    2. Enable MCAN Nodes on GESI and add transceiver node as per below in  k3-j721e-common-proc-board.dts file.

    Fullscreen GESI_CAN_Nodes.txt Download 
    transceiver_gesi: can-phy4 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&main_mcan4_gpio_pins_default>;
		standby-gpios = <&main_gpio0 60 GPIO_ACTIVE_HIGH>;
	};

/* Add pin mux under main_pmx0 reference */
main_mcan4_gpio_pins_default: main-mcan4-gpio-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x0F4, PIN_INPUT, 7) /* (AB24) PRG0_PRU0_GPO17.GPIO0_60 */
		>;
	};

main_mcan4_pins_default: main-mcan4-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x024, PIN_INPUT, 6) /* (AJ20) MCAN4_RX */
			J721E_IOPAD(0x020, PIN_OUTPUT, 6) /* (AE20) MCAN4_TX */
		>;
	};

main_mcan5_pins_default: main-mcan5-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x050, PIN_INPUT, 6) /* (AE21) MCAN5_RX */
			J721E_IOPAD(0x04C, PIN_OUTPUT, 6) /* (AJ21) MCAN5_TX */
		>;
	};

main_mcan6_pins_default: main-mcan6-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x06C, PIN_INPUT, 6) /* (AG21) MCAN6_RX */
			J721E_IOPAD(0x054, PIN_OUTPUT, 6) /* (AH21) MCAN6_TX */
		>;
	};

main_mcan7_pins_default: main-mcan7-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x078, PIN_INPUT, 6) /* (Y23) MCAN7_RX */
			J721E_IOPAD(0x074, PIN_OUTPUT, 6) /* (AC21) MCAN7_TX */
		>;
	};

main_mcan9_pins_default: main-mcan9-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x0D0, PIN_INPUT, 6) /* (AC27) MCAN9_RX */
			J721E_IOPAD(0x0CC, PIN_OUTPUT, 6) /* (AC28) MCAN9_TX */
		>;
	};

main_mcan11_pins_default: main-mcan11-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x120, PIN_INPUT, 6) /* (AA28) MCAN11_RX */
			J721E_IOPAD(0x11C, PIN_OUTPUT, 6) /* (AA24) MCAN11_TX */
		>;
	};



&main_mcan4 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_mcan4_pins_default>;
	phys = <&transceiver_gesi>;
};

&main_mcan5 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_mcan5_pins_default>;
	phys = <&transceiver_gesi>;
};

&main_mcan6 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_mcan6_pins_default>;
	phys = <&transceiver_gesi>;
};

&main_mcan7 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_mcan7pins_default>;
	phys = <&transceiver_gesi>;
};

&main_mcan9 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_mcan9_pins_default>;
	phys = <&transceiver_gesi>;
};

&main_mcan11 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_mcan11_pins_default>;
	phys = <&transceiver_gesi>;
};



    After making/adding above changes build dtbs and use the "k3-j721e-common-proc-board.dtb".


    Abdul Rehman said:
    I want to access it from RTOS.

    If you want to access from RTOS, you have to refer to RTOS examples and integrate those examples to your application and use.

    Abdul Rehman said:
    Also I want to enable all the ethernet ports as MAC ports so I can transfer the data externally through them.

    Using EthFw we can't enable all ports as MAC ports due to the resource limitation like UDMA Tx channels, Rx flows, MAC Address, please refer to EthFw user guide for more details about the resources on remote client cores.

    You can enable all ports as MAC only ports from linux by using native Linux driver for CPSW9g. Please refer to the FAQ [How to move to Native Linux driver] and run CPSW9g with Native Linux driver.

    For more detail about features supported with Native Linux driver and how to use, please refer to SDK Documentation of Native Driver.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 130 points

    Hi Sudheer,

    Thanks for the information. I have made the required changes.

    I am little confused on this

    After making/adding above changes build dtbs and use the "k3-j721e-common-proc-board.dtb".

    How can I build it? From which directory to I need to copy the file and to which location in RTOS directory.



    Can you please share commands for building a dts file.

    I am using vision apps https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/08_06_01_03/exports/docs/vision_apps/docs/user_guide/ENVIRONMENT_SETUP.html

    Best Regards,
    Abdul Rehman

  • 0 in reply to Abdul Rehman
    TI__Guru 64610 points

    Hi,

    Abdul Rehman said:
    After making/adding above changes build dtbs and use the "k3-j721e-common-proc-board.dtb".

    You have to download Linux SDK, and make changes mentioned in above note in k3-j721e-common-proc-board.dts file in "<Linux SDK>/board-support/linux-x.x.x/arch/arm64/boot/dts/ti/".

    Build Linux dts using following command from "<Linux SDK>".
    # make linux-dtbs

    For more details refer to Linux SDK documentation.

    Abdul Rehman said:
    How can I build it? From which directory to I need to copy the file and to which location in RTOS directory.

    After you build dts files, you will see generated binary in "<Linux SDK>/board-support/linux-x.x.x/arch/arm64/boot/dts/ti/" directory.

    You have to copy this updated binary to boot media "rootfs/boot/" directory and boot setup.

    As mentioned above, CAN channels enabled in A72 can't access from RTOS, those will be used form Linux A72.

    For RTOS based,, refer to RTOS examples and integrate to your application.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 130 points

    Build Linux dts using following command from "<Linux SDK>".
    # make linux-dtbs

    After running this command the file k3-j721e-common-proc-board.dtb remains same and there is no change in it. Do I need to change something in the config or make file?

  • 0 in reply to Abdul Rehman
    TI__Guru 64610 points

    Hi,

    Abdul Rehman said:
    After running this command the file k3-j721e-common-proc-board.dtb remains same and there is no change in it. Do I need to change something in the config or make file?

    No need of any configuration, After adding CNA channel nodes and transceiver node if you build device tree files "k3-j721e-common-proc-board.dtb"  will be generated again with CAN nodes, you can check the last updated date it should be present date and time.

    Note:
    You should use J721E Linux SDK for this.

    I have enabled CAN4 channel and tested at my side from A72 (Linux), working as expected.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 130 points

    Hi,

    If I want to deploy RTOS from vision_apps. How can utilize it RTOS. I got your point that its running on A72 linux. If I am deploying RTOS can I still see all the CAN channels through ifconfig -a? If not then what is the possible solution so I can use all the channels through some application. Do you have a basic application for test of all the CAN channels on RTOS?

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 130 points

    Hi,

    Here are my changes




    user@Ubuntu18:~/ti-processor-sdk-linux-j7-evm-08_06_00_11$ make linux-dtbs
    =====================================
    Building the Linux Kernel DTBs
    =====================================
    make -C /home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56 ARCH=arm64 CROSS_COMPILE=/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/linux-devkit/sysroots/x86_64-arago-linux/usr/bin/aarch64-none-linux-gnu- tisdk_j7-evm_defconfig
    make[1]: Entering directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    #
    # No change to .config
    #
    make[1]: Leaving directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Entering directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    DTC arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dtb
    arch/arm64/boot/dts/ti/k3-j721e-main.dtsi:2512.26-2524.4: ERROR (phandle_references): /bus@100000/can@2771000: Reference to non-existent node or label "main_mcan7pins_default"

    also defined at arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts:1220.13-1224.3
    ERROR: Input tree has errors, aborting (use -f to force output)
    scripts/Makefile.lib:328: recipe for target 'arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dtb' failed
    make[2]: *** [arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dtb] Error 2
    Makefile:1370: recipe for target 'ti/k3-j721e-common-proc-board.dtb' failed
    make[1]: *** [ti/k3-j721e-common-proc-board.dtb] Error 2
    make[1]: Leaving directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Entering directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    DTC arch/arm64/boot/dts/ti/k3-j721e-proc-board-tps65917.dtb
    arch/arm64/boot/dts/ti/k3-j721e-main.dtsi:2512.26-2524.4: ERROR (phandle_references): /bus@100000/can@2771000: Reference to non-existent node or label "main_mcan7pins_default"

    also defined at arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts:1220.13-1224.3
    ERROR: Input tree has errors, aborting (use -f to force output)
    scripts/Makefile.lib:328: recipe for target 'arch/arm64/boot/dts/ti/k3-j721e-proc-board-tps65917.dtb' failed
    make[2]: *** [arch/arm64/boot/dts/ti/k3-j721e-proc-board-tps65917.dtb] Error 2
    Makefile:1370: recipe for target 'ti/k3-j721e-proc-board-tps65917.dtb' failed
    make[1]: *** [ti/k3-j721e-proc-board-tps65917.dtb] Error 2
    make[1]: Leaving directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Entering directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Leaving directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Entering directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Leaving directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Entering directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Leaving directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Entering directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Leaving directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Entering directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Leaving directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Entering directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Leaving directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Entering directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Leaving directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Entering directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Leaving directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Entering directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Leaving directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Entering directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Leaving directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Entering directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Leaving directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Entering directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
    make[1]: Leaving directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'
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    make[1]: Leaving directory '/home/user/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56'



  • 0 in reply to Abdul Rehman
    TI__Guru 64610 points

    Hi,

    Abdul Rehman said:
    If I want to deploy RTOS from vision_apps. How can utilize it RTOS. I got your point that its running on A72 linux. If I am deploying RTOS can I still see all the CAN channels through ifconfig -a?

    RTOS deploy will be on R5F cores not on A72, Even with Vision Apps Linux will be loaded on A72.
    You can still view all CAN channel nodes in "ifconfig -a",  but for this you have to copy the dtb file generated with GESI CAN nodes and copy to boot media /rootfs/boot/ after preparing boot media ready using Vision apps scripts.

    Abdul Rehman said:
    Do you have a basic application for test of all the CAN channels on RTOS?
    Doredla Sudheer Kumar said:
    We have CAN examples in PDK from "<RTOS_SDK>/<pdk_xx>packages/ti/csl/example/mcan/mcanEvmLoopback" you can use those and test CAN channels.

    As pointed above, you can refer to the CAN example in PDK for testing CAN channels on R5F cores using RTOS.

    Best Regards,
    Sudheer

  • +1 in reply to Abdul Rehman
    TI__Guru 64610 points

    Hi,

    Abdul Rehman said:
    main_mcan7pins_default

    Sorry, there is a small mistake in MCAN7 node.
    Pin control should be "&main_mcan7_pins_default", please refer to below.



    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 130 points

    Hi Sudheer,

    Thank you for the help. I have managed to test all the CAN channels and they working fine. CAN issue is resolved for now.

    I want to enable all the ethernet ports as MAC ports in Linux A72.

    Steps I followed.

    1. RTOS Vision apps loaded.
    2. Updated dtb files for CAN.
    3. Run vision apps_init.sh file.
    4. run ifconfig -a

    I can only see share multicast ethernet ports that are used for A72 to R5f. However in the vision_apps/ethfw demo application the results looks like this



    How can I enable all the ports as MAC only? I read the documentation for enable as MAC only but its little confusing for me. I want to deploy vision_apps that is in the rtos directory and enable all the ports as MAC only so I can see all of them as shown above and also from ifconfig -a.


    My results looks like this.
    root@j7-evm:/opt/vision_apps# source ./vision_apps_init.sh
    root@j7-evm:/opt/vision_apps# [MCU2_0] 4.396076 s: CIO: Init ... Done !!!
    [MCU2_0] 4.396147 s: ### CPU Frequency = 1000000000 Hz
    [MCU2_0] 4.396192 s: CPU is running FreeRTOS
    [MCU2_0] 4.396222 s: APP: Init ... !!!
    [MCU2_0] 4.396246 s: SCICLIENT: Init ... !!!
    [MCU2_0] 4.396495 s: SCICLIENT: DMSC FW version [8.6.3--v08.06.03 (Chill Capybar]
    [MCU2_0] 4.396544 s: SCICLIENT: DMSC FW revision 0x8
    [MCU2_0] 4.396577 s: SCICLIENT: DMSC FW ABI revision 3.1
    [MCU2_0] 4.396614 s: SCICLIENT: Init ... Done !!!
    [MCU2_0] 4.396644 s: UDMA: Init ... !!!
    [MCU2_0] 4.397948 s: UDMA: Init ... Done !!!
    [MCU2_0] 4.398012 s: MEM: Init ... !!!
    [MCU2_0] 4.398057 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ d9000000 of size 16777216 bytes !!!
    [MCU2_0] 4.398134 s: MEM: Created heap (L3_MEM, id=1, flags=0x00000000) @ 3600000 of size 262144 bytes !!!
    [MCU2_0] 4.398196 s: MEM: Init ... Done !!!
    [MCU2_0] 4.398223 s: IPC: Init ... !!!
    [MCU2_0] 4.398285 s: IPC: 6 CPUs participating in IPC !!!
    [MCU2_0] 4.398333 s: IPC: Waiting for HLOS to be ready ... !!!
    [MCU2_0] 17.069683 s: IPC: HLOS is ready !!!
    [MCU2_0] 17.084858 s: IPC: Init ... Done !!!
    [MCU2_0] 17.084922 s: APP: Syncing with 5 CPUs ... !!!
    [MCU2_0] 17.219919 s: APP: Syncing with 5 CPUs ... Done !!!
    [MCU2_0] 17.220142 s: REMOTE_SERVICE: Init ... !!!
    [MCU2_0] 17.221730 s: REMOTE_SERVICE: Init ... Done !!!
    [MCU2_0] 17.221804 s: ETHFW: Init ... !!!
    [MCU2_0] 17.226913 s: Warning: Using 6 MAC address(es) from static pool
    [MCU2_0] 17.227028 s: ETHFW: Shared multicasts (software fanout):
    [MCU2_0] 17.227152 s: ETHFW: Reserved multicasts:
    [MCU2_0] 17.227193 s: 01:80:c2:00:00:0e
    [MCU2_0] 17.227240 s: 01:1b:19:00:00:00
    [MCU2_0] 17.227484 s: EnetMcm: CPSW_9G on MAIN NAVSS
    [MCU2_0] 17.236795 s: Mdio_open: MDIO manual mode enabled
    [MCU2_0] 17.239715 s: PHY 0 is alive
    [MCU2_0] 17.240020 s: PHY 3 is alive
    [MCU2_0] 17.240655 s: PHY 12 is alive
    [MCU2_0] 17.240902 s: PHY 15 is alive
    [MCU2_0] 17.241007 s: PHY 16 is alive
    [MCU2_0] 17.241113 s: PHY 17 is alive
    [MCU2_0] 17.241214 s: PHY 18 is alive
    [MCU2_0] 17.241315 s: PHY 19 is alive
    [MCU2_0] 17.241614 s: PHY 23 is alive
    [MCU2_0] 17.242699 s: EnetPhy_bindDriver: PHY 12: OUI:080028 Model:23 Ver:01 <-> 'dp83867' : OK
    [MCU2_0] 17.243205 s: EnetPhy_bindDriver: PHY 0: OUI:080028 Model:23 Ver:01 <-> 'dp83867' : OK
    [MCU2_0] 17.243688 s: EnetPhy_bindDriver: PHY 3: OUI:080028 Model:23 Ver:01 <-> 'dp83867' : OK
    [MCU2_0] 17.244173 s: EnetPhy_bindDriver: PHY 15: OUI:080028 Model:23 Ver:01 <-> 'dp83867' : OK
    [MCU2_0] 17.245895 s:
    [MCU2_0] ETHFW Version : 0.02.00
    [MCU2_0] 17.245967 s: ETHFW Build Date: Aug 4, 2023
    [MCU2_0] 17.246000 s: ETHFW Build Time: 12:44:55
    [MCU2_0] 17.246027 s: ETHFW Commit SHA:
    [MCU2_0] 17.246096 s: ETHFW: Init ... DONE !!!
    [MCU2_0] 17.246131 s: ETHFW: Remove server Init ... !!!
    [MCU2_0] 17.246307 s: CpswProxyServer: Virtual port configuration:
    [MCU2_0] 17.246363 s: mpu_1_0 <-> Switch port 0: mpu_1_0_ethswitch-device-0
    [MCU2_0] 17.246408 s: mcu_2_1 <-> Switch port 1: mcu_2_1_ethswitch-device-1
    [MCU2_0] 17.246450 s: mpu_1_0 <-> MAC port 1: mpu_1_0_ethmac-device-1
    [MCU2_0] 17.246491 s: mcu_2_1 <-> MAC port 4: mcu_2_1_ethmac-device-4
    [MCU2_0] 17.247503 s: CpswProxyServer: initialization completed (core: mcu2_0)
    [MCU2_0] 17.247573 s: ETHFW: Remove server Init ... DONE !!!
    [MCU2_0] 17.248710 s: Starting lwIP, local interface IP is dhcp-enabled
    [MCU2_0] 17.256644 s: Host MAC address: 70:ff:76:1d:92:c3
    [MCU2_0] 17.261021 s: [LWIPIF_LWIP] Enet LLD netif initialized successfully
    [

  • 0 in reply to Abdul Rehman
    TI__Guru 64610 points

    Hi,

    Thank you for confirmation of your CAN issue resolved.

    Doredla Sudheer Kumar said:
    Using EthFw we can't enable all ports as MAC ports due to the resource limitation like UDMA Tx channels, Rx flows, MAC Address, please refer to EthFw user guide for more details about the resources on remote client cores.

    You can enable all ports as MAC only ports from linux by using native Linux driver for CPSW9g. Please refer to the FAQ [How to move to Native Linux driver] and run CPSW9g with Native Linux driver.

    For more detail about features supported with Native Linux driver and how to use, please refer to SDK Documentation of Native Driver.

    As pointed above we can't enable all ports as MAC Only ports using EthFW.

    We have to use Linux native driver for CPSWnG for enabling native Linux driver please refer to FAQ pointed above.

    As you are using vision apps based rtos application by default EthFw will be part of vision application , you have to disable it from vision apps for native Linux driver usage. 

    Follow below steps for disabling EthFw from vision apps.

    Disable EthFw build flag from vision_apps/vision_apps_build_flags.mak as BUILD_ENABLE_ETHFW?= no and do a clean rebuild of vision_apps.

    After preparing the media card with above then apply device tree overlay for CPSWnG Native Linux driver as pointed in FAQ.

    Best Regards,

    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 130 points

    Hi Sudheer,

    Why I can't see all the MAC addresses for the ethernet ports when I am running vision_apps_init.sh

    If you can have a look into the picture from vision apps



    Here I have marker in yellow.

    However, when I am running the same application. I can only see 2 MAC address. 

    [MCU2_0] 17.221804 s: ETHFW: Init ... !!!
    [MCU2_0] 17.226913 s: Warning: Using 6 MAC address(es) from static pool
    [MCU2_0] 17.227028 s: ETHFW: Shared multicasts (software fanout):
    [MCU2_0] 17.227152 s: ETHFW: Reserved multicasts:
    [MCU2_0] 17.227193 s: 01:80:c2:00:00:0e
    [MCU2_0] 17.227240 s: 01:1b:19:00:00:00
    [MCU2_0] 17.227484 s: EnetMcm: CPSW_9G on MAIN NAVSS
    [MCU2_0] 17.236795 s: Mdio_open: MDIO manual mode enabled
    [MCU2_0] 17.239715 s: PHY 0 is alive
    [MCU2_0] 17.240020 s: PHY 3 is alive
    [MCU2_0] 17.240655 s: PHY 12 is alive
    [MCU2_0] 17.240902 s: PHY 15 is alive
    [MCU2_0] 17.241007 s: PHY 16 is alive
    [MCU2_0] 17.241113 s: PHY 17 is alive
    [MCU2_0] 17.241214 s: PHY 18 is alive
    [MCU2_0] 17.241315 s: PHY 19 is alive
    [MCU2_0] 17.241614 s: PHY 23 is alive

    Maybe I can explain my problem little bit. I am using vision_apps and want to send/receive data to multiple ethernet ports. For that I need separate IP for each port which I can easily set by assigning a static IP in the network file. I am not bound to use RTOS or LINUX. However, I am bound to deploy vision_apps. What is the best possible solution?

    Best Regards,
    Abdul Rehman


  • 0 in reply to Abdul Rehman
    TI__Guru 64610 points

    Hi,

    Abdul Rehman said:
    Why I can't see all the MAC addresses for the ethernet ports when I am running vision_apps_init.sh

    Vision Apps integrates EthFw and running on MCU2_0 (RTOS).
    EthFw configures two ports as MAC only Ports (Port-1 mapped to A72, Port-4 mapped to MCU2_1) and rest all are part of Switch port.
    MAC address assign will be each interface not for MAC port and by default it will map one MAC only Port to A72 and one Switch interface to A72 so, 2 MAC address will be used by A72.
    Similarly one MAC port mapped to MCU2_1 client and one switch port mapped to MCU2_1 so, 2 MAC address will be used by MCU2_1.
    Internal Switch port on MCU2_0 will use one MAC Address.

    For switch interface you can communicate to the device connected any of switch ports (as per above Port-2,3,5,6,7,8 are switch ports and 1,4 are MAC only ports).

    If you want to configure all ports as MAC only, you have to disable switch ports and map the ports to any of client that needs more resources than reserved in EthFw.

    So, suggested to go for Native Linux driver approach by default Linux driver treats each port as individually MAC only port and you can see 8 interfaces from ifconfig -a command on A72.

    Information related to EthFw can be found from Ethernet Firmware User Guide.

    Abdul Rehman said:
    I am not bound to use RTOS or LINUX. However, I am bound to deploy vision_apps. What is the best possible solution?

    As I have above please follow FAQ [How to move to Native Linux driver] and enable native Linux driver for CPSW9G, and there is no other solution for this.

    Have you followed FAQ for enabling native Linux driver for CPSWnG?

    Best Regards,
    Sudheer


  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 130 points

    Hi Sudheer,

    Thanks for the quick reply. I have build a fresh vision_apps without ethfw and copied prebuilt dtbo files available at FAQs. It doesn't work. Now I am trying to compile it as mentioned in the FAQs. However, I am little confused with the name of dtbo.

    user@Ubuntu18:~/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56$ make ARCH=arm64 CROSS_COMPILE=aarch64-none-linux-gnu-k3-j721e-quad-port-eth-exp.dtbo
    arch/arm64/Makefile:25: ld does not support --fix-cortex-a53-843419; kernel may be susceptible to erratum
    make: aarch64-none-linux-gnu-k3-j721e-quad-port-eth-exp.dtbogcc: Command not found
    SYNC include/config/auto.conf.cmd
    scripts/Kconfig.include:39: compiler 'aarch64-none-linux-gnu-k3-j721e-quad-port-eth-exp.dtbogcc' not found
    scripts/kconfig/Makefile:71: recipe for target 'syncconfig' failed
    make[2]: *** [syncconfig] Error 1
    Makefile:606: recipe for target 'syncconfig' failed
    make[1]: *** [syncconfig] Error 2
    Makefile:723: recipe for target 'include/config/auto.conf.cmd' failed
    make: *** [include/config/auto.conf.cmd] Error 2
    user@Ubuntu18:~/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56$ make ARCH=arm64 CROSS_COMPILE=aarch64-none-linux-gnu-k3-j721e-quad-port-eth-exp
    arch/arm64/Makefile:25: ld does not support --fix-cortex-a53-843419; kernel may be susceptible to erratum
    make: aarch64-none-linux-gnu-k3-j721e-quad-port-eth-expgcc: Command not found
    SYNC include/config/auto.conf.cmd
    scripts/Kconfig.include:39: compiler 'aarch64-none-linux-gnu-k3-j721e-quad-port-eth-expgcc' not found
    scripts/kconfig/Makefile:71: recipe for target 'syncconfig' failed
    make[2]: *** [syncconfig] Error 1
    Makefile:606: recipe for target 'syncconfig' failed
    make[1]: *** [syncconfig] Error 2
    Makefile:723: recipe for target 'include/config/auto.conf.cmd' failed
    make: *** [include/config/auto.conf.cmd] Error 2
    user@Ubuntu18:~/ti-processor-sdk-linux-j7-evm-08_06_00_11/board-support/linux-5.10.162+gitAUTOINC+76b3e88d56-g76b3e88d56$ make ARCH=arm64 CROSS_COMPILE=aarch64-none-linux-gnu-k3-j721e
    arch/arm64/Makefile:25: ld does not support --fix-cortex-a53-843419; kernel may be susceptible to erratum
    make: aarch64-none-linux-gnu-k3-j721egcc: Command not found
    SYNC include/config/auto.conf.cmd
    scripts/Kconfig.include:39: compiler 'aarch64-none-linux-gnu-k3-j721egcc' not found
    scripts/kconfig/Makefile:71: recipe for target 'syncconfig' failed
    make[2]: *** [syncconfig] Error 1
    Makefile:606: recipe for target 'syncconfig' failed
    make[1]: *** [syncconfig] Error 2
    Makefile:723: recipe for target 'include/config/auto.conf.cmd' failed
    make: *** [include/config/auto.conf.cmd] Error 2

  • 0 in reply to Abdul Rehman
    TI__Guru 64610 points

    Hi,

    Abdul Rehman said:
    make ARCH=arm64 CROSS_COMPILE=aarch64-none-linux-gnu-k3-j721e-quad-port-eth-exp.dtbo

    As you are using TDA4VM and GESI card, you can use below command to build device tree overlay.

    make ARCH=arm64 CROSS_COMPILE=aarch64-none-linux-gnu- ti/k3-j721e-gesi-exp-board.dtbo
    It will provide access to 4 ports on GESI card for other 4 Ports on Quad Enet card enable "ti/k3-j721e-quad-port-eth-exp.dtbo" as well

    Note: 
    Take care of port numbers enabling from GESI and Quad device tree files.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 130 points

    Hi Sudheer,

    I have managed to load the dtbo files but it still only enable 4 ports on gesi board.

    root@j7-evm:/opt/vision_apps# ifconfig |grep eth
    ether 02:42:dd:2f:6a:a6 txqueuelen 0 (Ethernet)
    eth0: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500 metric 1
    ether 34:08:e1:5b:66:4d txqueuelen 1000 (Ethernet)
    eth1: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500 metric 1
    ether 70:ff:76:1f:0a:f4 txqueuelen 1000 (Ethernet)
    eth2: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500 metric 1
    ether 70:ff:76:1f:0a:f5 txqueuelen 1000 (Ethernet)
    eth3: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500 metric 1
    ether 70:ff:76:1f:0a:f6 txqueuelen 1000 (Ethernet)
    eth4: flags=4163<UP,BROADCAST,RUNNING,MULTICAST> mtu 1500 metric 1
    ether 70:ff:76:1f:0a:f7 txqueuelen 1000 (Ethernet)

    My uenv.txt

    psdk_setup_file=.psdk_setup
    check_psdk_setup=load mmc 1:1 ${loadaddr} ${psdk_setup_file}

    # Reset to the default environment
    do_psdk_setup=env default -f -a; saveenv

    # If not previously configured, then configure the environment and indicate this by writing a file
    uenvcmd=if run check_psdk_setup; then echo "Already setup."; else run do_psdk_setup; mw.b ${loadaddr} 0 1; fatwrite mmc 1:1 ${loadaddr} .psdk_setup 1; reset; fi

    dorprocboot=1
    name_overlays=k3-j721e-vision-apps.dtbo k3-j721e-quad-port-eth-exp.dtbo k3-j721e-gesi-exp-board.dtbo

    /rootfs/boot  structure

  • 0 in reply to Abdul Rehman
    TI__Guru 64610 points

    Hi,

    Abdul Rehman said:
    I have managed to load the dtbo files but it still only enable 4 ports on gesi board.
    Doredla Sudheer Kumar said:
    make ARCH=arm64 CROSS_COMPILE=aarch64-none-linux-gnu- ti/k3-j721e-gesi-exp-board.dtbo
    It will provide access to 4 ports on GESI card for other 4 Ports on Quad Enet card enable "ti/k3-j721e-quad-port-eth-exp.dtbo" as well

    Note: 
    Take care of port numbers enabling from GESI and Quad device tree files.

    As I have pointed above, you have to take care of Port numbers in the device tree files of GESI and Quad ethernet both will point to the 1st 4 ports.

    You can change port numbers in one of device tress files from 1-4 to 5-8 so that you can view 8 ports with ifconfig -a.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 130 points

    Hi Sudheer,

    I have changed the following in dts files.

    k3-j721e-gesi-exp-board.dts

    Changed


    Do I have to change this also?


    Are there any other changes?


    Best Regards,
    Abdul Rehman

  • 0 in reply to Abdul Rehman
    TI__Guru 64610 points

    Hi,


    Use same numbers for ethernetX and port@X in above.

    You have to change Pin Mux as per your Board and port number as required.

    If your are using J721E EVM, you have make changes in both GESI and QUAD expansion device tress files as per below.

    GESI overlay file:

    1. Enable Port numbers 1,3,4,8 in RGMII Mode.
    2. Select RGMII Pin mux also as per port numbers.
    3. Remove disabling of other CPSW Ports, as you want to enable all 8 Ports.

    QUAD overlay files:

    1. Enable Port numbers 2,5,6,7 in QSGMII Mode (default Port-2 is Main Node and rest of all are sub modes in QSGMII)
    2. Remove disabling of other CPSW ports.

    Use CPSW Port numbers also as pointed above specific to overlay file.

    Build both overlays and use generated device tree binaries and update uEnv.txt file with overlay file names and boot Board.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 130 points

    Hi Sudheer,

    GESI:

    / {
    fragment@102 {
    target-path = "/";
    __overlay__ {
    aliases {
    ethernet5 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
    ethernet6 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
    ethernet7 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
    ethernet8 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8";
    };
    };
    };
    };

    &cpsw0 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&mdio_pins_default
    &rgmii1_pins_default
    &rgmii2_pins_default
    &rgmii3_pins_default
    &rgmii4_pins_default>;
    };

    &cpsw0_port1 {
    phy-handle = <&cpsw9g_phy12>;
    phy-mode = "rgmii-rxid";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 1>;
    };

    &cpsw0_port3 {
    phy-handle = <&cpsw9g_phy15>;
    phy-mode = "rgmii-rxid";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 2>;
    };

    &cpsw0_port4 {
    phy-handle = <&cpsw9g_phy0>;
    phy-mode = "rgmii-rxid";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 3>;
    };

    &cpsw0_port8 {
    phy-handle = <&cpsw9g_phy3>;
    phy-mode = "rgmii-rxid";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 4>;
    };

    Quad port:


    / {
    fragment@102 {
    target-path = "/";
    __overlay__ {
    aliases {
    ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
    ethernet5 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5";
    ethernet6 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6";
    ethernet7 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7";
    };
    };
    };
    };

    &cpsw0 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&mdio_pins_default>;
    };

    &cpsw0_port2 {
    phy-handle = <&cpsw9g_phy0>;
    phy-mode = "qsgmii";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 1>;
    };

    &cpsw0_port5 {
    phy-handle = <&cpsw9g_phy1>;
    phy-mode = "qsgmii";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 2>;
    };

    &cpsw0_port6 {
    phy-handle = <&cpsw9g_phy2>;
    phy-mode = "qsgmii";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 3>;
    };

    &cpsw0_port7 {
    phy-handle = <&cpsw9g_phy3>;
    phy-mode = "qsgmii";
    mac-address = [00 00 00 00 00 00];
    phys = <&cpsw0_phy_gmii_sel 4>;
    };

    /*
    &cpsw0_port5 {
    status = "disabled";
    };

    &cpsw0_port6 {
    status = "disabled";
    };

    &cpsw0_port7 {
    status = "disabled";
    };

    &cpsw0_port8 {
    status = "disabled";
    };
    */

    Is it correct? It seems like there is a clast for 2 ports in gesi and quad eth. I bold both of them. Please let me know if it is correct.

    Best Regards,
    Abdul Rehman

  • 0 in reply to Abdul Rehman
    TI__Guru 64610 points

    Hi,

    As I have pointed above you have to update the Pin Mux for RGMII Ports-1,3,4,8 

    &rgmii1_pins_default
    &rgmii2_pins_default
    &rgmii3_pins_default
    &rgmii4_pins_default>;

    Instead of RGMII2 you have to add Pin Mux for Port-8 and reference from above.
    Also, PHY nodes "cpsw9g_phy3" use port numbers as per Ports mapped for the overlay (as pointed above).

    Note:
    Please use "cpsw9g_mdio" once and merge the content of both files under this mdio node.

    It would be better to use single overlay file and merge the content of both files into single file.

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 130 points

    Hi,

    I have changed the files. Please have a look at the files and it would be great if you can do the necessary changes.

    GESI:

    // SPDX-License-Identifier: GPL-2.0
/**
 * DT Overlay for CPSW9G in RGMII mode using J7 GESI EXP BRD board with
 * J721E board.
 *
 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/pinctrl/k3.h>

/ {
	fragment@102 {
		target-path = "/";
		__overlay__ {
			aliases {
				ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
				ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
				ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
				ethernet8 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8";
			};
		};
	};
};

&cpsw0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins_default
		     &rgmii1_pins_default
		     &rgmii3_pins_default
		     &rgmii4_pins_default
		     &rgmii8_pins_default>;
};

&cpsw0_port1 {
	phy-handle = <&cpsw9g_phy12>;
	phy-mode = "rgmii-rxid";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 1>;
};

&cpsw0_port3 {
	phy-handle = <&cpsw9g_phy15>;
	phy-mode = "rgmii-rxid";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 2>;
};

&cpsw0_port4 {
	phy-handle = <&cpsw9g_phy0>;
	phy-mode = "rgmii-rxid";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 3>;
};

&cpsw0_port8 {
	phy-handle = <&cpsw9g_phy3>;
	phy-mode = "rgmii-rxid";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 4>;
};

/*
&cpsw0_port5 {
	status = "disabled";
};

&cpsw0_port6 {
	status = "disabled";
};

&cpsw0_port7 {
	status = "disabled";
};

&cpsw0_port8 {
	status = "disabled";
};
*/
&cpsw9g_mdio {
	bus_freq = <1000000>;
	#address-cells = <1>;
	#size-cells = <0>;

	cpsw9g_phy0: ethernet-phy@0 {
		reg = <0>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		ti,min-output-impedance;
	};
	cpsw9g_phy3: ethernet-phy@3 {
		reg = <3>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		ti,min-output-impedance;
	};
	cpsw9g_phy12: ethernet-phy@12 {
		reg = <12>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		ti,min-output-impedance;
	};
	cpsw9g_phy15: ethernet-phy@15 {
		reg = <15>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
		ti,min-output-impedance;
	};
};

&cpsw9g_virt_mac {
	status = "disabled";
};

&exp1 {
	p15-hog {
		/* P15 - EXP_MUX2 */
		gpio-hog;
		gpios = <13 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "EXP_MUX2";
	};

	p16-hog {
		/* P16 - EXP_MUX3 */
		gpio-hog;
		gpios = <14 GPIO_ACTIVE_HIGH>;
		output-high;
		line-name = "EXP_MUX3";
	};
};

&main_pmx0 {
	mdio_pins_default: mdio-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
			J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
		>;
	};

	rgmii1_pins_default: rgmii1-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x4, PIN_INPUT, 4) /* (AC23) PRG1_PRU0_GPO0.RGMII1_RD0 */
			J721E_IOPAD(0x8, PIN_INPUT, 4) /* (AG22) PRG1_PRU0_GPO1.RGMII1_RD1 */
			J721E_IOPAD(0xc, PIN_INPUT, 4) /* (AF22) PRG1_PRU0_GPO2.RGMII1_RD2 */
			J721E_IOPAD(0x10, PIN_INPUT, 4) /* (AJ23) PRG1_PRU0_GPO3.RGMII1_RD3 */
			J721E_IOPAD(0x1c, PIN_INPUT, 4) /* (AD22) PRG1_PRU0_GPO6.RGMII1_RXC */
			J721E_IOPAD(0x14, PIN_INPUT, 4) /* (AH23) PRG1_PRU0_GPO4.RGMII1_RX_CTL */
			J721E_IOPAD(0x30, PIN_OUTPUT, 4) /* (AF24) PRG1_PRU0_GPO11.RGMII1_TD0 */
			J721E_IOPAD(0x34, PIN_OUTPUT, 4) /* (AJ24) PRG1_PRU0_GPO12.RGMII1_TD1 */
			J721E_IOPAD(0x38, PIN_OUTPUT, 4) /* (AG24) PRG1_PRU0_GPO13.RGMII1_TD2 */
			J721E_IOPAD(0x3c, PIN_OUTPUT, 4) /* (AD24) PRG1_PRU0_GPO14.RGMII1_TD3 */
			J721E_IOPAD(0x44, PIN_OUTPUT, 4) /* (AE24) PRG1_PRU0_GPO16.RGMII1_TXC */
			J721E_IOPAD(0x40, PIN_OUTPUT, 4) /* (AC24) PRG1_PRU0_GPO15.RGMII1_TX_CTL */
		>;
	};

	rgmii2_pins_default: rgmii2-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x58, PIN_INPUT, 4) /* (AE22) PRG1_PRU1_GPO0.RGMII2_RD0 */
			J721E_IOPAD(0x5c, PIN_INPUT, 4) /* (AG23) PRG1_PRU1_GPO1.RGMII2_RD1 */
			J721E_IOPAD(0x60, PIN_INPUT, 4) /* (AF23) PRG1_PRU1_GPO2.RGMII2_RD2 */
			J721E_IOPAD(0x64, PIN_INPUT, 4) /* (AD23) PRG1_PRU1_GPO3.RGMII2_RD3 */
			J721E_IOPAD(0x70, PIN_INPUT, 4) /* (AE23) PRG1_PRU1_GPO6.RGMII2_RXC */
			J721E_IOPAD(0x68, PIN_INPUT, 4) /* (AH24) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
			J721E_IOPAD(0x84, PIN_OUTPUT, 4) /* (AJ25) PRG1_PRU1_GPO11.RGMII2_TD0 */
			J721E_IOPAD(0x88, PIN_OUTPUT, 4) /* (AH25) PRG1_PRU1_GPO12.RGMII2_TD1 */
			J721E_IOPAD(0x8c, PIN_OUTPUT, 4) /* (AG25) PRG1_PRU1_GPO13.RGMII2_TD2 */
			J721E_IOPAD(0x90, PIN_OUTPUT, 4) /* (AH26) PRG1_PRU1_GPO14.RGMII2_TD3 */
			J721E_IOPAD(0x98, PIN_OUTPUT, 4) /* (AJ26) PRG1_PRU1_GPO16.RGMII2_TXC */
			J721E_IOPAD(0x94, PIN_OUTPUT, 4) /* (AJ27) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
		>;
	};

	rgmii3_pins_default: rgmii3-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0xb0, PIN_INPUT, 4) /* (AF28) PRG0_PRU0_GPO0.RGMII3_RD0 */
			J721E_IOPAD(0xb4, PIN_INPUT, 4) /* (AE28) PRG0_PRU0_GPO1.RGMII3_RD1 */
			J721E_IOPAD(0xb8, PIN_INPUT, 4) /* (AE27) PRG0_PRU0_GPO2.RGMII3_RD2 */
			J721E_IOPAD(0xbc, PIN_INPUT, 4) /* (AD26) PRG0_PRU0_GPO3.RGMII3_RD3 */
			J721E_IOPAD(0xc8, PIN_INPUT, 4) /* (AE26) PRG0_PRU0_GPO6.RGMII3_RXC */
			J721E_IOPAD(0xc0, PIN_INPUT, 4) /* (AD25) PRG0_PRU0_GPO4.RGMII3_RX_CTL */
			J721E_IOPAD(0xdc, PIN_OUTPUT, 4) /* (AJ28) PRG0_PRU0_GPO11.RGMII3_TD0 */
			J721E_IOPAD(0xe0, PIN_OUTPUT, 4) /* (AH27) PRG0_PRU0_GPO12.RGMII3_TD1 */
			J721E_IOPAD(0xe4, PIN_OUTPUT, 4) /* (AH29) PRG0_PRU0_GPO13.RGMII3_TD2 */
			J721E_IOPAD(0xe8, PIN_OUTPUT, 4) /* (AG28) PRG0_PRU0_GPO14.RGMII3_TD3 */
			J721E_IOPAD(0xf0, PIN_OUTPUT, 4) /* (AH28) PRG0_PRU0_GPO16.RGMII3_TXC */
			J721E_IOPAD(0xec, PIN_OUTPUT, 4) /* (AG27) PRG0_PRU0_GPO15.RGMII3_TX_CTL */
		>;
	};

	rgmii4_pins_default: rgmii4-pins-default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x100, PIN_INPUT, 4) /* (AE29) PRG0_PRU1_GPO0.RGMII4_RD0 */
			J721E_IOPAD(0x104, PIN_INPUT, 4) /* (AD28) PRG0_PRU1_GPO1.RGMII4_RD1 */
			J721E_IOPAD(0x108, PIN_INPUT, 4) /* (AD27) PRG0_PRU1_GPO2.RGMII4_RD2 */
			J721E_IOPAD(0x10c, PIN_INPUT, 4) /* (AC25) PRG0_PRU1_GPO3.RGMII4_RD3 */
			J721E_IOPAD(0x118, PIN_INPUT, 4) /* (AC26) PRG0_PRU1_GPO6.RGMII4_RXC */
			J721E_IOPAD(0x110, PIN_INPUT, 4) /* (AD29) PRG0_PRU1_GPO4.RGMII4_RX_CTL */
			J721E_IOPAD(0x12c, PIN_OUTPUT, 4) /* (AG26) PRG0_PRU1_GPO11.RGMII4_TD0 */
			J721E_IOPAD(0x130, PIN_OUTPUT, 4) /* (AF27) PRG0_PRU1_GPO12.RGMII4_TD1 */
			J721E_IOPAD(0x134, PIN_OUTPUT, 4) /* (AF26) PRG0_PRU1_GPO13.RGMII4_TD2 */
			J721E_IOPAD(0x138, PIN_OUTPUT, 4) /* (AE25) PRG0_PRU1_GPO14.RGMII4_TD3 */
			J721E_IOPAD(0x140, PIN_OUTPUT, 4) /* (AG29) PRG0_PRU1_GPO16.RGMII4_TXC */
			J721E_IOPAD(0x13c, PIN_OUTPUT, 4) /* (AF29) PRG0_PRU1_GPO15.RGMII4_TX_CTL */
		>;
	};
};

&main_r5fss0_core0 {
	firmware-name = "pdk-ipc/ipc_echo_test_mcu2_0_release_strip.xer5f";
};


    Quad-port:
    // SPDX-License-Identifier: GPL-2.0
/**
 * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
 * J721E board.
 *
 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/k3.h>

/ {
	fragment@102 {
		target-path = "/";
		__overlay__ {
			aliases {
				ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
				ethernet5 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5";
				ethernet6 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6";
				ethernet7 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7";
			};
		};
	};
};

&cpsw0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins_default>;
};

&cpsw0_port2 {
	phy-handle = <&cpsw9g_phy0>;
	phy-mode = "qsgmii";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 1>;
};

&cpsw0_port5 {
	phy-handle = <&cpsw9g_phy1>;
	phy-mode = "qsgmii";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 2>;
};

&cpsw0_port6 {
	phy-handle = <&cpsw9g_phy2>;
	phy-mode = "qsgmii";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 3>;
};

&cpsw0_port7 {
	phy-handle = <&cpsw9g_phy3>;
	phy-mode = "qsgmii";
	mac-address = [00 00 00 00 00 00];
	phys = <&cpsw0_phy_gmii_sel 4>;
};

/*
&cpsw0_port5 {
	status = "disabled";
};

&cpsw0_port6 {
	status = "disabled";
};

&cpsw0_port7 {
	status = "disabled";
};

&cpsw0_port8 {
	status = "disabled";
};
*/
&cpsw9g_mdio {
	bus_freq = <1000000>;
	reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
	reset-post-delay-us = <120000>;
	#address-cells = <1>;
	#size-cells = <0>;

	cpsw9g_phy0: ethernet-phy@17 {
		reg = <17>;
	};
	cpsw9g_phy1: ethernet-phy@16 {
		reg = <16>;
	};
	cpsw9g_phy2: ethernet-phy@18 {
		reg = <18>;
	};
	cpsw9g_phy3: ethernet-phy@19 {
		reg = <19>;
	};
};

&cpsw9g_virt_mac {
	status = "disabled";
};

&exp2 {
	qsgmii-line-hog {
		gpio-hog;
		gpios = <16 GPIO_ACTIVE_HIGH>;
		output-low;
		line-name = "qsgmii-pwrdn-line";
	};
};

&main_pmx0 {
	mdio_pins_default: mdio_pins_default {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
			J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
		>;
	};
};

&main_r5fss0_core0 {
	firmware-name = "pdk-ipc/ipc_echo_test_mcu2_0_release_strip.xer5f";
};


    Best Regards,
    Abdul Rehman

  • +1 in reply to Abdul Rehman
    TI__Guru 64610 points

    Hi,

    Abdul Rehman said:
    I have changed the files. Please have a look at the files and it would be great if you can do the necessary changes.

    Please refer to the FAQ [How to Move to Native Linux Driver], where we have added device tree file for enabling 8 Ports in TDAVM.

    Best Regards,
    Sudheer