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The internal memory is all single-cycle data access. This is mentioned on the first page of the data sheet under the "Enhanced Memory System" bullet.
For instruction accesses everything must go through the L1P. So for a "hit" in L1P the instructions will execute in a single cycle. If there is a "miss" in L1P then you occur a 2-cycle miss penalty (documented in Section 2.5 of the 6727B datasheet, sprs370b).
