Hi,
Please find our below questions with respect to J721E SDK.
Kindly find the attachment for a brief idea of our pipeline for the clarifications raised below.
1) Whether all the 3 CSI Rx ports shall be consumed or do we have restrictions when used together with other peripherals (Eg Whether DSS and CSI2 are sharing same HW pins or ports). If yes, what are those combinations of limitations?
2) What would be differences between free RTOS and safe RTOS while migrating from freeRTOS to safeRTOS based on 9.1 SDK in one of the cores of R5F?
3) Whether interfaces shall remain the same for the low level drivers(Eg I2C, CSI2) when migrating to ASIL B qualification?
4) The accelerators and its drivers (interfaces) VPAC, DMPAC are mentioned as safety qualified. Whether they are ASIL B qualified?
5) Any plans to have IPC communication as ASIL B qualified?
6) In order to qualify one of the R5F cores to be ASIL B, do we have safety manuals and SAN(Safety application notes) describing MMU protection, FFI, ECC protection for the internal memories?
7) Could you please also confirm whether in Open VX safety qualification roadmap whether APIs would be modified as part of qualification?
8) Whether there would be separate TI Drivers required for AVB Stack/RTP stack in freeRTOS/safeRTOS or it would be coming along with TI PDK package.
In the below image, the ones highlighted in blue color below are either accelerators/drivers from TI. So we would like to know whether we would have the safety qualification and checkers for each of them.
If possible could you please share us a matrix describing the safety qualification.
Kindly revert back for further clarifications or queries.
