Part Number: TMS320C6678
Hi Team,
The customer's scheme is as follows:
The FPGA side writes data in NWIRTE-R format to the DSP side, and the DSP receives the data and returns the data and operating status using REPSONE WITH DATA. The DSP side now controls the LSU registers in the direct I/O mode of SRIO under bare core, it sets whether the Ftype=Srio_Ftype_response;ttype=Srio_Ttype_response_response_payload mode can pass through CSL The CSL_SRIO_SetLSUTransfer(hSrio, LSU_number, &tparams) function implements the response with data data transmission.
The DSP is doing an in-house loopback test: data write to the NWIRTE-R followed by a write to the Srio_Ttype_response_response_payload. Now the NWIRTE-R is sent successfully, but the transaction with response with data is sent with CSL_SRIO_GetLSUCompleteCode(hSrio, LSU_number, TransactionID, &uiCompleteCode, &context) returns the error uiCompleteCode=-4 status. The error may be caused by an unsupported packet class type or by the occurrence of at least one LSU encoding which is invalid.
/* wait loopback complete time set as 10ms, base on cpu freq as 1000MHz */
timeout = 10000000;
/* 1.3 caculate the read and write buffer for srio transfer address */
//1.3A read-write buffer that computes the wrio transfer address
srio_trans_src = (uint32_t *)t_buff_global;
// srio_trans_dst = (uint32_t *)r_buff_global;
srio_trans_dst= (uint32_t *)TARGET_ADDRESS;
printf("NREAD srio_trans_src= %d,srio_trans_dst=%d\n",srio_trans_src , srio_trans_dst);
printf("NREAD srio_trans_src= 0x%x,srio_trans_dst=0x%x\n",srio_trans_src , srio_trans_dst);
//cuix add r_buff
/* 1.4 set transfer parameters, srio nread test, devmem_buff -> r_buff */
memset((void *)&tparams, 0, sizeof(tparams));
tparams.rapidIOLSB = (uint32_t)srio_trans_src;
tparams.dspAddress = (uint32_t)srio_trans_dst;
tparams.bytecount = transfer_size;
//Srio_Ftype_RESPONSE I/O Transaction
//Ftype:w_format_type=Srio_Ftype_RESPONSE (13) ttpye:Srio_Ttype_Response_RESPONSE_PAYLOAD(8)
tparams.ftype = Srio_Ftype_RESPONSE ; //Format fType
tparams.ttype =Srio_Ttype_Response_RESPONSE_PAYLOAD ;
//id of the target device to be sent
tparams.dstID = REMOTE_DEVICEID1_8BIT;
tparams.outPortID = SRIO_PORT;
tparams.idSize = 0;
/* wait LSU have available shadow register */
while(1) {
if (CSL_SRIO_IsLSUFull (hSrio, LSU_Number) == FALSE)
break;
}
/* Get the LSU Context and Transaction Information. */
CSL_SRIO_GetLSUContextTransaction(hSrio, LSU_Number,
&contextBit, &transactionID);
transStart = _itoll(TSCH, TSCL);
/* start srio transfer */
CSL_SRIO_SetLSUTransfer(hSrio, LSU_Number, &tparams);
/* wait for a transfer completion interrupt occur */
while(timeout) {
CSL_SRIO_GetLSUCompletionCode(hSrio, LSU_Number, transactionID,
&uiCompletionCode, &context);
if(context == contextBit) {
/* disable pending transactions */
transactionID = 0xFF;
contextBit = 0xFF;
if(uiCompletionCode != 0) {
status = -1;
printf("SRIO transfer have error completed code %d\r\n", -(uiCompletionCode));
goto err_transfer;
}
break;
} else {
timeout--;
/* delay 1 cpu cyle */
asm (" nop");
}
}
if(timeout == 0) {
/* if transfer timeout occurs, return error status */
status = -1;
printf("SRIO transfer timeout\r\n");
goto err_transfer;
}
/* Calculate srio transfer used time */
transCost = _itoll(TSCH, TSCL) - transStart;
r_time = transCost;
/* Calculate srio transfer read rate */
//Srio_Ttype_Request_NREAD read data
r_rate = (float)transfer_size * main_pll_freq / r_time / 1024 / 1024 / 1024 * 8;
w_rate_total += w_rate;
r_rate_total += r_rate;
for(i = 0; i < transfer_size; i++) {
printf("test addr: 0x%x, dst addr: 0x%x\r\n", \
w_buff_global[i], r_buff_global[i]);
if(w_buff_global[i] != r_buff_global[i]) {
printf(" src addr: 0x%x, dst addr: 0x%x\r\n", \
(uint32_t)&w_buff_global[i], (uint32_t)&r_buff_global[i]);
err_count++;
if(err_count == 1) {
printf("Frist Err occurred src addr: 0x%x, dst addr: 0x%x\r\n", \
(uint32_t)&w_buff_global[i], (uint32_t)&r_buff_global[i]);
printf("dst val: 0x%x, ", r_buff_global[i]);
printf("expet val: 0x%x\r\n", w_buff_global[i]);
}
}
1) Is the above scheme theoretically feasible? But TI does not have a case with a response with data transaction.
a. If so, how to try to modify the uiCompleteCode=-4 state?
b. if not, could you help give some suggestions for improvement?
2) Can the DSP side use SRIO to write data to the fixed address of the FPGA using the Srio_Ttype_response_response_response_payload method of the direct I/O?
Could you please help look into this case? Thanks.
Best Regards,
Cherry