LP-AM263: SDL PBIST exit sequence

Hi Andy,

The AM263x MCUs are targeted towards safety-critical applications, and it is critical for any failures in the on-chip SRAM to be identified before it is used for safety-critical functions. These MCUs support Programmable Built-In Self-Test (PBIST) mechanism that is used to test each on-chip SRAM module for faults. The PBIST is usually run on device start-up as it is a destructive test and all contents of the tested SRAM module are overwritten during the test.

The contents of the selected memory before the test will be completely lost. User software must take care of data backup if required. Typically the PBIST tests are carried out at the
beginning of application software.

If cache memory is selected to be part of the PBIST test then the contents will become incoherent with respect to the TCM and level 2 memory after the PBIST test. The cache will need to be invalidated before cache can be enabled for use by the CPU. 

if the ECC is used in the cache, the ECC should be enabled (programming the CEC bits in the Auxiliary Control Register) before invalidating the cache, to ensure that the correct error code bits are calculated when the cache is invalidated. I think that user software should take care of this action. 

Hi QJ, Thanks for the response. The information is good but I'm still not clear on the details needed to implement the exit sequence.

I am developing a safety-critical application that runs on both R5FSS0 and R5FSS1 in lockstep mode. I want to use the PBIST at startup to test for any SRAM faults in both r5 subsystems.
If the application code running on R5F0 calls the following function:
```
SDL_PBIST_selfTest(
      SDL_PBIST_INST_TOP, SDL_PBIST_TEST,
      100000000U, &PBISTResult);
```
then I want the R5F0 application code to recover the R5FSS1 subsystem afterwards.

Would these steps cover all of the recovery that R5FSS1 needs?
 1. enable ECC for used R5FSS1 memory regions
 2. invalidate cache for these R5FSS1 memory regions
 3. Reload R5FSS1 program and data memory from storage to RAM. (Similar to what the SBL does).
 
Thank you,
 -Andy

Hi Andy,

About #3, I need to check if the ECC is turned off during the PBIST, then come back to you later.

HI Andy,

After the PBIST test, the RAM's ECC space is also program with a data pattern. It is not a valid ECC value of the RAM content. The hardware memory initialization is needed after PBIST test. The hardware mechanism allows an application to program the memory arrays with error detection capability to a known state based on their error detection scheme (ECC).

The MSS_ATCMx_MEM_INIT, MSS_BTCMx_MEM_INIT, MSS_L2_MEM_INIT registers are use to initiate the memory HW initialization.

Hi QJ, Thank you. I will attempt to implement it on my own and return with questions.

Would it be possible to ask the SDL team to add library functions or examples that implement the exit sequence in a future release?