AM3354: LCD Display Disturbances during SD card Access

Hello Hideaki

Thank you for the query.

Let me review the inputs.

Can you confirm if the issue happens on a specific board or on multiple boards.

Could you also please confirm if  all the required power supplies and the clock provided are as per the data sheet recommendation.

Regards,

Sreenivasa

Hi Sreenivasa,

Thank you for your reply.

Kallikuppa Sreenivasa said:

Can you confirm if the issue happens on a specific board or on multiple boards.

Yes, the issue happens on multiple boards.

Kallikuppa Sreenivasa said:

Could you also please confirm if  all the required power supplies and the clock provided are as per the data sheet recommendation.

They doublechecked the design and confirmed there is no problem.

Please provide your answer to the following questions, especially to the 2).

Hideaki Matsumoto said:

1)    As the first phenomenon of LCD display disturbance, LCD Data becomes Low for a certain period of time.

       They presume that this is the result of DMA (Direct Memory Access) conflict between the timing of reading/writing the SD card and the drawing processing of the LCD.

       Is their understanding correct?

 

2)    They also found similar LCD display disturbances in TI's FAQ. AM3359 Timing - Processors forum - Processors - TI E2E support forums

       Is it correct to think that this issue can also be resolved by adjusting the OCP_CONFIG register setting value?

 

3)    The LCD Data becomes Low (= black screen display) for one LCD drawing cycle in the next drawing cycle when the LCD Data is delayed by several us compared with when it is normal.

       Is this the specification of the AM3354?

Thanks and regards,

Hideaki

Hello Hideaki

Than you for the query.

Based on your inputs i understand it happens on multiple boards (not sure if this happens on all the boards or across multiple batches) and intermittently when SD card is being read.

There is no issue seen when the AD card is not accessed.

Can you help confirm is customer has series resistors for the clock signals.

Are the LCD and SD card signals routed closely?

Regards,

Sreenivasa

Hi Sreenivasa,

Could you PLEASE give them some your feedback to their question 2) below. They think that it's very similar issue with their issue.

Hideaki Matsumoto said:

2)    They also found similar LCD display disturbances in TI's FAQ. AM3359 Timing - Processors forum - Processors - TI E2E support forums

       Is it correct to think that this issue can also be resolved by adjusting the OCP_CONFIG register setting value?

Here are their answers to your quesions below.

Kallikuppa Sreenivasa said:

Can you help confirm is customer has series resistors for the clock signals.

They put the 33 ohm dumping resister on the CLK line between CPU and LVDS IC and the common mode inductor on the line between LVDS IC and LCD.

Kallikuppa Sreenivasa said:

Are the LCD and SD card signals routed closely?

Actually, the signal lines of LCD and that of SD card are crossed but on the different layers, so they don’t think they’re not close.

SD Data signal :    Layer 1

LCD Signal :         Layer 6

Boot SD signal :    Layer 8

Regards,

Hideaki

• Hello Hideaki

  Than you  The issue in the thread discussed seems to have been observed. 

  In customer case my understanding is that the issue is intermittent.  Let me know if the understanding is correct.

  Hideaki Matsumoto said:

  2)    They also found similar LCD display disturbances in TI's FAQ. AM3359 Timing - Processors forum - Processors - TI E2E support forums

         Is it correct to think that this issue can also be resolved by adjusting the OCP_CONFIG register setting value?

  Hi James,

   

  I suppose your DE signal is connected to the LCD_AC_BIAS_EN pin of AM335X? Is this effect stable, (i.e. once the system starts the display is either good or bad), or does the display change on the fly? Do you see this on one board only or on multiple boards?
• I forgot to ask where have you measured the signals - on the processor side or after the LVDS?
• Yes, the DE pin is connected to lcd_ac_bias_en. 

  Yes, it is absolutely stable. If it boots up with the problem, the problem remains all the while I am using it. If it boots up OK, it remains OK. The only way I can change it is to either 1) reboot, or 2) execute ts_calibrate. After a few times executing ts_calibrate, it will toggle the display to screen offset or correct.

  I'm measuring the signals between the processor and the LVDS chip.

  Why does this happen? How can I debug it? Any help/advice is welcome!

  Are you getting any DMA underflow interrupts or frame sync lost interrupts?

  I am used to high level programming on Linux, I don't know how to check those interrupts. Can you point me to where I can get information on how to see those interrupts?

  Regards,

  Sreenivasa

Hello Hideaki

The issue in the attached thread seems to have been observed consistently. 

In customer case my understanding is that the issue is intermittent.  The issues is not being observed every time SD card is accessed. Let me know if the understanding is correct.

It would be a good idea for customer to check implementing the solution discussed in the thread if possible.

Regards,

Sreenivasa

Hello Hideaki

Please refer inputs i received from the device expert

I suspect a signal integrity, power integrity issue, or both.  It most likely occurs when lots of IOs are changing from 0 to 1 or 1 to 0  at the same time. The large inrush of current required to change all the signals at once is causing power quality issues.  This could be caused by not implementing low loop inductance connections to their decoupling capacitors, the power traces between the power source and the device may be too inductive, or the power supply may not have good transient response.

 They will need to use a very high bandwidth scope and probe to measure power supply noise directly on the device power pins and look for fast noise transients that drop below the ROC values for short periods of time.

Regards,

Sreenivasa