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AM5706: What is the BYPASS-bit of IPUx_UNICACHE_CFG Register ?

Hideaki Matsumoto
Genius 9130 points
Part Number: AM5706

Hi,

 

My customer has some questions about the specification of “AMMU-UNICACHE” of Dual Cortex-M4 IPU Subsystem on AM5706.

 

Q1) Could you tell them what “BYPASS-bit” of IPUx_UNICACHE_CFG Register means ?

    The Register manual describes as “0x0: Everything is non-cacheable.／0x1: Everything is cacheable.”. Does it mean that the IPU cache will not be enabled unless this bit is set ON ?

    (Referring to the page 1748 in AM571x and AM570x TRM)

 

 

Q2) When “BYPASS-bit is set ON, memory access to the spaces other than those registered in AMMU is disabled.

    They confirmed below.

-  Accessing by program code => BusFault occurred

-  Memory dump by ICE => Read impossible.

    Is this operation the specification of this device ?  If so, could you tell them any workaround ?

    Also, they have confirmed that the area other than the AMMU registration space as well can be accessed when “BYPASS-bit” is set OFF.

 

< Information >

AM5706

CCS v8

TI v18.1.2.LTS

HW AM5706 Custom Board

SW pdk_am57xx_1_0_11

   bios_6_76_00_08

XDCTools 3.50.3.33

ICE　Lauterbach

 

Thanks and regards,

Hideaki

  • 0
    TI__Mastermind 31955 points

    Hello Matsumoto-san,

    Sorry for the delay, I will address this by next week.

    -Josue

  • 0 in reply to Josue Zamitiz-Ayala
    TI__Mastermind 31955 points

    Hello Matsumoto-san,

    I will post some of the information I have gathered internally:

    Q1) ""bypass bit means cache allocation won't happen, therefore a write or a read will always come from outside of the unicache array"

    "The ammu function will still happen even if the caches are by passed.  The ammu along with possible translation adds attributes to transactions (like read/write/execute, cache-ability).  The bypass is of the cache attribute behavior not the ammu translations and protections"

    "An M4 core has a arch-local-address mapping which the AMMU allows conversion of to IPU local addresses.  Without a mapping an M4 local may not hit IPU targets, it also allows some permissions.  in a simialr way the L2 mmu translates IPU local addresses to L3 addresses.  You program up the two MMUs to get at what you want.   In the local or global space.  The m4 can't see everyting otherwise given its arch-mem-map."

    See Picture:

                

    "A person needs to look at the M4 ARM TRM to understand its constraints, you then look at the IPU address mapping, and you use the AMMU to fix it up, you then if you like use the L2-MMU to map in any L3 addresses ranges you need or want to protect."