TDA4VH-Q1: SDL bist function with boot_app on J784S4_EVM

zhisong zheng

Part Number: TDA4VH-Q1

Hi Ti expert:

I implement SDL bist function from SDL example from the generated image.There has two images bist_example_r5f_baremetal_multicore_image.appimage and bist_example_r5f_baremetal_release.appimage.

I get bist_example_r5f_baremetal_multicore_image.appimage include one MCU1_0 test app and C71 clearClecSerureCalim and another one MCU1_0 app doesn't work.From the uart boot log ,I can see C71 and MCU1_0 boot from SBL.

So the problems has happened,In the regular project the custom C71 code need to boot from MCU1_0 boot_app in the MCU1_0 app,I need implement bist function and boot custom C71.

I try move clear secure code to custom C71 code,it seems work well,but when the PBIST and LBIST functions are done,try to boot A72 and Main R5 ,c71 are failed no any uart log.I use the XDS110 try to connect debug but failed.

Can you give me any suggestion or example can implement two function from the SDK? by the way the SDK9.0 /mcusw/mcuss_demos/boot_app_mcu_rtos can you show the selftest report?

over 2 years ago

0 KB over 2 years ago

TI__Guru** 120881 points

Hi,

I'm having troubles following what is and is not working in above tests. In regards to the C7x clearClecSerureClaim, the high level reasoning for having that image is below:

For A72 / C7x / Analytics - PBIST tests to run they require that the CLEC be programmed from the MCU R5.
From SDK 8.6 onwards, the MCU R5 is by default i non-secure mode, and can no longer modify the CLEC.
A C7x image has been created to allow for clearing of the "secure claim bit" to allow MCU R5 to access CLEC
The MCU R5 can then program the CLEC as it wants, whether it be for A72 / C7x / Analytics.

Regards,

0 zhisong zheng over 2 years ago in reply to KB

Intellectual 431 points

Yes I can see these words from SDL notes and understand.

Can you tell me the boot_app examples can finish all the BIST test in SDK8.6?

I thought TI demo can't implement these requirements.Can you confirm again?

And show the test boot_app with bist log,looking forward to a valid answer next time

Thanks.

0 KB over 2 years ago in reply to zhisong zheng

TI__Guru** 120881 points

Hi,

The SDL Release notes indicate any known issues in a given SDK: 1.1. Release Notes - 01_00_00 — Software Diagnostics Library (SDL) - J784S4 User Guide

The SDL example section has logs for each test are shown including the BIST tests. These tests are the stand alone test images:

3.8. BIST Safety Example — Software Diagnostics Library (SDL) - J784S4 User Guide

In regard to an integrated SDL test within the boot application, to my knowledge this was not tested as part of TI verification. The boot application support was moved to the pdk/packages/ti/boot/sbl/example/boot_app location and SDL integration has yet to occur.

Regards,

0 Kangjia Dong over 1 year ago in reply to KB

TI__Intellectual 2215 points

Hi Expert,
Customer have other issue need further clarify.

0 zhisong zheng over 1 year ago in reply to KB

Intellectual 431 points

My requirement is very simple,I need a demo project bist with boot_app in J784S4_evm.I understand TI no example provided at this stage.My project need this function in our product.

0 KB over 1 year ago in reply to zhisong zheng

TI__Guru** 120881 points

With the assumption that SDK 9.0 is in use, the PDK SBL contains both the SBL and a Boot app example, which should function as-is.

ti-processor-sdk-rtos-j784s4-evm-09_00_01_01/pdk_j784s4_09_00_01_04/packages/ti/boot/sbl
5. Bootloader (SBL) — Platform Development Kit (PDK) - J784S4 User Guide (ti.com)

If there are issues with the SBL and/or SBL boot application example in SDK 9.0, please provide logs.

The alternative approach is to use the boot application in mcusw, with the PDK SBL.

ti-processor-sdk-rtos-j784s4-evm-09_00_01_01/mcusw/mcuss_demos/boot_app_mcu_rtos
MCUSW: CAN Response Application

If there are issues/questions, with either of the boot applications please let us know.

In either of these boot applications, SDL code can be integrated.

Regards,

0 zhisong zheng over 1 year ago in reply to KB

Intellectual 431 points

I already integrated it once,only two cases can pass,you should do once reproduce,this is a very obvious problem.You should do it once and tell me the result.

0 KB over 1 year ago in reply to zhisong zheng

TI__Guru** 120881 points

Hi,

TI team will check for availability of any patches that can be shared.

In parallel if you could provide logs, or a description of what issues you are facing with the integration effort this would be helpful.

Regards,

0 Josiitaa RL over 1 year ago in reply to zhisong zheng

TI__Mastermind 41196 points

Hi,

As discussed on the internal mail thread, the C7x secure claim bit is an issue, and will effect performance and complexity on SDK 8.6.

I will provide a partial patch for SDK 8.6, where a subset of the PBIST / LBIST tests are shown to be functional in SBL boot application, in two weeks.

Although, it is recommended that you move to SDK 9.1 for production, to avoid the C7x Secure Claim bit issue.

Regards,

Josiitaa

0 zhisong zheng over 1 year ago in reply to Josiitaa RL

Intellectual 431 points

Thanks

0 Josiitaa RL over 1 year ago in reply to zhisong zheng

TI__Mastermind 41196 points

Hi,

Could you also post the failures that you are getting, while I try and integrate the tests?

Regards,

Josiitaa

0 zhisong zheng over 1 year ago in reply to Josiitaa RL

Intellectual 431 points

I do PBIST_runTest

parameter 3 sub case i = 1 found error

parameter 7 sub case 1 found error

0 Josiitaa RL over 1 year ago in reply to zhisong zheng

TI__Mastermind 41196 points

Hi,

We have identified some issues with the flow sequence of the MCUSW BootApp on SDK 8.6, which have been resolved in SDK 9.0. As a result, there have been some integration failures with BIST.

However, we have alternative solutions available:

1. We could either work with the SBL boot flow on SDK 8.6. I have an experimental patch that you could refer to and test BIST with SBL.

2. I can work on integrating BIST with the MCUSW BootApp on SDK 9.0.

Note: Both these approaches are expected to work partially as clarified earlier, where a subset of the PBIST / LBIST tests are shown to be functional in MCUSW boot application.

Please let me know which option you prefer and we will proceed accordingly. I apologize for any inconvenience caused.

Regards,

Josiitaa

0 zhisong zheng over 1 year ago in reply to Josiitaa RL

Intellectual 431 points

HI!

Thanks for your reply!

We have obtained the latest package (SDK9.1) for relevant testing. Verified using BIST function alone, but the boot function has not been validated after BIST.

Thank you!

0 Josiitaa RL over 1 year ago in reply to zhisong zheng

TI__Mastermind 41196 points

Hi,

I have reproduced the issue on SDK 9.1. I see that the boot flow halts when loading lateapp2. I am debugging the issue and will get back to you in a couple of weeks.

Regards,

Josiitaa

0 Kangjia Dong over 1 year ago in reply to Josiitaa RL

TI__Intellectual 2215 points

update the issue status: Current SBL+QNX do bist has been finished and verified on EVM but SBL+ Linux will be stuck on the kernel mount rootfs.

Fullscreen a72_log.txt Download

NOTICE:  BL31: Built : 09:34:15, Aug 24 2023
ERROR:   GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC: 
I/TC: OP-TEE version: 4.0.0 (gcc version 11.4.0 (GCC)) #1 Fri Oct 20 18:29:31 UTC 2023 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: SYSFW ABI: 3.1 (firmware rev 0x0009 '9.1.2--v09.01.02 (Kool Koala)')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Fixing SA2UL firewall owner for GP device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot
[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x411fd080]
[    0.000000] Linux version 6.1.46-g5892b80d6b (oe-user@oe-host) (aarch64-oe-linux-gcc (GCC) 11.4.0, GNU ld (GNU Binutils) 2.38.20220708) #1 SMP PREEMPT Mon Nov 27 16:11:04 UTC 2023
[    0.000000] Machine model: Texas Instruments J784S4 EVM
[    0.000000] earlycon: ns16550a0 at MMIO32 0x0000000002880000 (options '')
[    0.000000] printk: bootconsole [ns16550a0] enabled
[    0.000000] efi: UEFI not found.
[    0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000f90000000, size 1792 MiB
[    0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a0000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a0100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a0100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a1000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a1100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a1100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a2000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a2100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a2100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a3000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a3000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a3100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a3100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a4000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a4100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a4100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a5000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a5000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a5100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a5100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a6000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a6000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a6100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a6100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a7000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node r5f-dma-memory@a7000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a7100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node r5f-memory@a7100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a8000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node c71-dma-memory@a8000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a8100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node c71-memory@a8100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a9000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node c71-dma-memory@a9000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000a9100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node c71-memory@a9100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000aa000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node c71-dma-memory@aa000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000aa100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node c71-memory@aa100000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000ab000000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node c71-dma-memory@ab000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created DMA memory pool at 0x00000000ab100000, size 15 MiB
[    0.000000] OF: reserved mem: initialized node c71-memory@ab100000, compatible id shared-dma-pool
[    0.000000] Zone ranges:
[    0.000000]   DMA      [mem 0x0000000080000000-0x00000000ffffffff]
[    0.000000]   DMA32    empty
[    0.000000]   Normal   [mem 0x0000000100000000-0x0000000fffffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000080000000-0x000000009e7fffff]
[    0.000000]   node   0: [mem 0x000000009e800000-0x00000000abffffff]
[    0.000000]   node   0: [mem 0x00000000ac000000-0x00000000ffffffff]
[    0.000000]   node   0: [mem 0x0000000880000000-0x0000000fffffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x0000000fffffffff]
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: Trusted OS migration not required
[    0.000000] psci: SMC Calling Convention v1.4
[    0.000000] percpu: Embedded 19 pages/cpu s38376 r8192 d31256 u77824
[    0.000000] Detected PIPT I-cache on CPU0
[    0.000000] CPU features: detected: GIC system register CPU interface
[    0.000000] CPU features: detected: Spectre-v3a
[    0.000000] CPU features: detected: Spectre-BHB
[    0.000000] CPU features: kernel page table isolation forced ON by KASLR
[    0.000000] CPU features: detected: Kernel page table isolation (KPTI)
[    0.000000] CPU features: detected: ARM erratum 1742098
[    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
[    0.000000] alternatives: applying boot alternatives
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 8257536
[    0.000000] Kernel command line: console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02880000 root=/dev/mmcblk1p2 rw rootfstype=ext4 rootwait
[    0.000000] Dentry cache hash table entries: 4194304 (order: 13, 33554432 bytes, linear)
[    0.000000] Inode-cache hash table entries: 2097152 (order: 12, 16777216 bytes, linear)
[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[    0.000000] software IO TLB: area num 8.
[    0.000000] software IO TLB: mapped [mem 0x00000000fbfff000-0x00000000fffff000] (64MB)
[    0.000000] Memory: 30771668K/33554432K available (12352K kernel code, 1266K rwdata, 4028K rodata, 2112K init, 432K bss, 947756K reserved, 1835008K cma-reserved)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
[    0.000000] rcu: Preemptible hierarchical RCU implementation.
[    0.000000] rcu:     RCU event tracing is enabled.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
[    0.000000]  Trampoline variant of Tasks RCU enabled.
[    0.000000]  Tracing variant of Tasks RCU enabled.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GICv3: [Firmware Bug]: GICR region 0x0000000001900000 has overlapping address
[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode
[    0.000000] GICv3: 960 SPIs implemented
[    0.000000] GICv3: 0 Extended SPIs implemented
[    0.000000] Root IRQ handler: gic_handle_irq
[    0.000000] GICv3: GICv3 features: 16 PPIs
[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000001900000
[    0.000000] ITS [mem 0x01820000-0x0182ffff]
[    0.000000] GIC: enabling workaround for ITS: Socionext Synquacer pre-ITS
[    0.000000] ITS@0x0000000001820000: Devices Table too large, reduce ids 20->19
[    0.000000] ITS@0x0000000001820000: allocated 524288 Devices @880800000 (flat, esz 8, psz 64K, shr 0)
[    0.000000] ITS: using cache flushing for cmd queue
[    0.000000] GICv3: using LPI property table @0x0000000880050000
[    0.000000] GIC: using cache flushing for LPI property table
[    0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000880060000
[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
[    0.000000] arch_timer: cp15 timer(s) running at 200.00MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0x3ffffffffffffff max_cycles: 0x2e2049d3e8, max_idle_ns: 440795210634 ns
[    0.000000] sched_clock: 58 bits at 200MHz, resolution 5ns, wraps every 4398046511102ns
[    0.010561] Console: colour dummy device 80x25
[    0.016280] Calibrating delay loop (skipped), value calculated using timer frequency.. 400.00 BogoMIPS (lpj=800000)
[    0.029620] pid_max: default: 32768 minimum: 301
[    0.035547] LSM: Security Framework initializing
[    0.041575] Mount-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
[    0.051344] Mountpoint-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
[    0.062907] cblist_init_generic: Setting adjustable number of callback queues.
[    0.072174] cblist_init_generic: Setting shift to 3 and lim to 1.
[    0.080020] cblist_init_generic: Setting adjustable number of callback queues.
[    0.089255] cblist_init_generic: Setting shift to 3 and lim to 1.
[    0.097151] rcu: Hierarchical SRCU implementation.
[    0.103274] rcu:     Max phase no-delay instances is 1000.
[    0.110180] Platform MSI: msi-controller@1820000 domain created
[    0.118009] PCI/MSI: /bus@100000/interrupt-controller@1800000/msi-controller@1820000 domain created
[    0.129832] EFI services will not be available.
[    0.135938] smp: Bringing up secondary CPUs ...
ERROR:   GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC: Secondary CPU 1 initializing
I/TC: Secondary CPU 1 switching to normal world boot
ERROR:   GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC: Secondary CPU 2 initializing
I/TC: Secondary CPU 2 switching to normal world boot
ERROR:   GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC: Secondary CPU 3 initializing
I/TC: Secondary CPU 3 switching to normal world boot
ERROR:   GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC: Secondary CPU 4 initializing
I/TC: Secondary CPU 4 switching to normal world boot
ERROR:   GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC: Secondary CPU 5 initializing
I/TC: Secondary CPU 5 switching to normal world boot
ERROR:   GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC: Secondary CPU 6 initializing
I/TC: Secondary CPU 6 switching to normal world boot
ERROR:   GTC_CNTFID0 is 0! Assuming 200000000 Hz. Fix Bootloader
I/TC: Secondary CPU 7 initializing
I/TC: Secondary CPU 7 switching to normal world boot
[    0.159618] Detected PIPT I-cache on CPU1
[    0.159703] GICv3: CPU1: found redistributor 1 region 0:0x0000000001920000
[    0.159720] GICv3: CPU1: using allocated LPI pending table @0x0000000880070000
[    0.159765] CPU1: Booted secondary processor 0x0000000001 [0x411fd080]
[    0.177705] Detected PIPT I-cache on CPU2
[    0.177781] GICv3: CPU2: found redistributor 2 region 0:0x0000000001940000
[    0.177797] GICv3: CPU2: using allocated LPI pending table @0x0000000880080000
[    0.177830] CPU2: Booted secondary processor 0x0000000002 [0x411fd080]
[    0.195712] Detected PIPT I-cache on CPU3
[    0.195784] GICv3: CPU3: found redistributor 3 region 0:0x0000000001960000
[    0.195801] GICv3: CPU3: using allocated LPI pending table @0x0000000880090000
[    0.195832] CPU3: Booted secondary processor 0x0000000003 [0x411fd080]
[    0.217964] Detected PIPT I-cache on CPU4
[    0.222022] GICv3: CPU4: found redistributor 100 region 0:0x0000000001980000
[    0.222615] GICv3: CPU4: using allocated LPI pending table @0x00000008800a0000
[    0.223730] CPU4: Booted secondary processor 0x0000000100 [0x411fd080]
[    0.250106] Detected PIPT I-cache on CPU5
[    0.254218] GICv3: CPU5: found redistributor 101 region 0:0x00000000019a0000
[    0.254802] GICv3: CPU5: using allocated LPI pending table @0x00000008800b0000
[    0.255851] CPU5: Booted secondary processor 0x0000000101 [0x411fd080]
[    0.281614] Detected PIPT I-cache on CPU6
[    0.285813] GICv3: CPU6: found redistributor 102 region 0:0x00000000019c0000
[    0.286421] GICv3: CPU6: using allocated LPI pending table @0x00000008800c0000
[    0.287459] CPU6: Booted secondary processor 0x0000000102 [0x411fd080]
[    0.313209] Detected PIPT I-cache on CPU7
[    0.317555] GICv3: CPU7: found redistributor 103 region 0:0x00000000019e0000
[    0.318146] GICv3: CPU7: using allocated LPI pending table @0x00000008800d0000
[    0.319202] CPU7: Booted secondary processor 0x0000000103 [0x411fd080]
[    0.322410] smp: Brought up 1 node, 8 CPUs
[    0.549287] SMP: Total of 8 processors activated.
[    0.555363] CPU features: detected: 32-bit EL0 Support
[    0.562013] CPU features: detected: CRC32 instructions
[    0.569781] CPU: All CPU(s) started at EL2
[    0.575033] alternatives: applying system-wide alternatives
[    0.587137] devtmpfs: initialized
[    0.608046] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.620565] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
[    0.668080] pinctrl core: initialized pinctrl subsystem
[    0.675337] DMI not present or invalid.
[    0.681079] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[    0.693587] DMA: preallocated 4096 KiB GFP_KERNEL pool for atomic allocations
[    0.703709] DMA: preallocated 4096 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
[    0.714764] DMA: preallocated 4096 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
[    0.725145] audit: initializing netlink subsys (disabled)
[    0.732386] audit: type=2000 audit(0.504:1): state=initialized audit_enabled=0 res=1
[    0.732770] thermal_sys: Registered thermal governor 'step_wise'
[    0.742327] thermal_sys: Registered thermal governor 'power_allocator'
[    0.751068] cpuidle: using governor menu
[    0.764603] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.775920] ASID allocator initialised with 32768 entries
[    0.795550] platform 4800000.dsi: Fixed dependency cycle(s) with /bus@100000/dss@4a00000
[    0.805932] platform 4800000.dsi: Fixed dependency cycle(s) with /bus@100000/i2c@2040000/dsi-edp-bridge@2c
[    0.818479] platform a000000.dp-bridge: Fixed dependency cycle(s) with /bus@100000/dss@4a00000
[    0.832268] platform a000000.dp-bridge: Fixed dependency cycle(s) with /dp0-connector
[    0.843540] KASLR enabled
[    0.853622] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
[    0.862365] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
[    0.870415] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
[    0.879173] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
[    0.887201] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
[    0.895892] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
[    0.903917] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
[    0.912599] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
[    0.925155] k3-chipinfo 43000014.chipid: Family:J784S4 rev:SR1.0 JTAGID[0x0bb8002f] Detected
[    0.938619] iommu: Default domain type: Translated 
[    0.944899] iommu: DMA domain TLB invalidation policy: strict mode 
[    0.953180] SCSI subsystem initialized
[    0.958487] usbcore: registered new interface driver usbfs
[    0.965576] usbcore: registered new interface driver hub
[    0.972409] usbcore: registered new device driver usb
[    0.979340] pps_core: LinuxPPS API ver. 1 registered
[    0.985723] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.997423] PTP clock support registered
[    1.002584] EDAC MC: Ver: 3.0.0
[    1.008223] FPGA manager framework
[    1.012678] Advanced Linux Sound Architecture Driver Initialized.
[    1.022807] clocksource: Switched to clocksource arch_sys_counter
[    1.031276] VFS: Disk quotas dquot_6.6.0
[    1.036387] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    1.050106] NET: Registered PF_INET protocol family
[    1.057775] IP idents hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[    1.074002] tcp_listen_portaddr_hash hash table entries: 16384 (order: 6, 262144 bytes, linear)
[    1.085748] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
[    1.095702] TCP established hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[    1.107172] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
[    1.117878] TCP: Hash tables configured (established 262144 bind 65536)
[    1.126530] UDP hash table entries: 16384 (order: 7, 524288 bytes, linear)
[    1.135727] UDP-Lite hash table entries: 16384 (order: 7, 524288 bytes, linear)
[    1.145645] NET: Registered PF_UNIX/PF_LOCAL protocol family
[    1.156113] RPC: Registered named UNIX socket transport module.
[    1.163835] RPC: Registered udp transport module.
[    1.169856] RPC: Registered tcp transport module.
[    1.175875] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    1.184112] NET: Registered PF_XDP protocol family
[    1.190381] PCI: CLS 0 bytes, default 64
[    1.210298] hw perfevents: enabled with armv8_cortex_a72 PMU driver, 7 counters available
[    1.223315] Initialise system trusted keyrings
[    1.229417] workingset: timestamp_bits=46 max_order=23 bucket_order=0
[    1.240827] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    1.248757] NFS: Registering the id_resolver key type
[    1.255246] Key type id_resolver registered
[    1.260590] Key type id_legacy registered
[    1.265747] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    1.274313] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
[    1.308718] Key type asymmetric registered
[    1.313948] Asymmetric key parser 'x509' registered
[    1.320230] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
[    1.330689] io scheduler mq-deadline registered
[    1.336510] io scheduler kyber registered
[    1.439903] pinctrl-single 4301c000.pinctrl: 13 pins, size 52
[    1.447745] pinctrl-single 4301c038.pinctrl: 11 pins, size 44
[    1.455553] pinctrl-single 4301c068.pinctrl: 72 pins, size 288
[    1.463244] pinctrl-single 4301c190.pinctrl: 1 pins, size 4
[    1.470914] pinctrl-single 11c000.pinctrl: 72 pins, size 288
[    1.479261] pinctrl-single a40000.pinctrl: 512 pins, size 2048
[    1.496873] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[    1.547994] loop: module loaded
[    1.553430] megasas: 07.719.03.00-rc1
[    1.560695] tun: Universal TUN/TAP device driver, 1.6
[    1.567788] thunder_xcv, ver 1.0
[    1.571937] thunder_bgx, ver 1.0
[    1.576073] nicpf, ver 1.0
[    1.579666] e1000: Intel(R) PRO/1000 Network Driver
[    1.585895] e1000: Copyright (c) 1999-2006 Intel Corporation.
[    1.593256] e1000e: Intel(R) PRO/1000 Network Driver
[    1.599594] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
[    1.607171] igb: Intel(R) Gigabit Ethernet Network Driver
[    1.614064] igb: Copyright (c) 2007-2014 Intel Corporation.
[    1.621204] igbvf: Intel(R) Gigabit Virtual Function Network Driver
[    1.629210] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
[    1.636870] sky2: driver version 1.30
[    1.642164] VFIO - User Level meta-driver version: 0.3
[    1.649401] usbcore: registered new interface driver usb-storage
[    1.657559] i2c_dev: i2c /dev entries driver
[    1.663916] sdhci: Secure Digital Host Controller Interface driver
[    1.671822] sdhci: Copyright(c) Pierre Ossman
[    1.677567] sdhci-pltfm: SDHCI platform and OF driver helper
[    1.689169] ledtrig-cpu: registered to indicate activity on CPUs
[    1.697252] SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
[    1.705791] usbcore: registered new interface driver usbhid
[    1.712911] usbhid: USB HID core driver
[    1.718770] optee: probing for conduit method.
I/TC: Reserved shared memory is enabled
I/TC: Dynamic shared memory is enabled
I/TC: Normal World virtualization support is disabled
I/TC: Asynchronous notifications are disabled
[    1.724480] optee: revision 4.0 (2a5b1d12)
[    1.745114] optee: dynamic shared memory is enabled
[    1.757221] optee: initialized driver
[    1.764146] Initializing XFRM netlink socket
[    1.769644] NET: Registered PF_PACKET protocol family
[    1.776169] Key type dns_resolver registered
[    1.782010] registered taskstats version 1
[    1.787275] Loading compiled-in X.509 certificates
[    1.831084] ti-sci 44083000.system-controller: ABI: 3.1 (firmware rev 0x0009 '9.1.2--v09.01.02 (Kool Koala)')
[    1.897568] omap_i2c 42120000.i2c: bus 1 rev0.12 at 400 kHz
[    1.934058] pca953x 0-0020: supply vcc not found, using dummy regulator
[    1.950234] pca953x 0-0020: using no AI
[    2.005746] pca953x 0-0022: supply vcc not found, using dummy regulator
[    2.020450] pca953x 0-0022: using AI
[    2.043622] omap_i2c 2000000.i2c: bus 0 rev0.12 at 400 kHz
[    2.094477] pca953x 2-0020: supply vcc not found, using dummy regulator
[    2.109699] pca953x 2-0020: using no AI
[    2.174443] omap_i2c 2040000.i2c: bus 2 rev0.12 at 400 kHz
[    2.236193] pca953x 3-0020: supply vcc not found, using dummy regulator
[    2.251484] pca953x 3-0020: using no AI
[    2.293197] omap_i2c 2050000.i2c: bus 3 rev0.12 at 400 kHz
[    2.305762] ti-sci-intr 42200000.interrupt-controller: Interrupt Router 177 domain created
[    2.317184] ti-sci-intr bus@100000:interrupt-controller@a00000: Interrupt Router 10 domain created
[    2.328936] ti-sci-intr 310e0000.interrupt-controller: Interrupt Router 283 domain created
[    2.340605] ti-sci-inta 33d00000.msi-controller: Interrupt Aggregator domain 321 created
[    2.362507] ti-udma 311a0000.dma-controller: Number of rings: 48
[    2.371566] ti-udma 311a0000.dma-controller: Channels: 24 (bchan: 0, tchan: 8, rchan: 16)
[    2.383667] k3-ringacc 2b800000.ringacc: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:328
[    2.396044] k3-ringacc 2b800000.ringacc: dma-ring-reset-quirk: disabled
[    2.404496] k3-ringacc 2b800000.ringacc: RA Proxy rev. 66349100, num_proxies:64
[    2.416206] k3-ringacc 3c000000.ringacc: Ring Accelerator probed rings:1024, gp-rings[878,128] sci-dev-id:315
[    2.428931] k3-ringacc 3c000000.ringacc: dma-ring-reset-quirk: disabled
[    2.437381] k3-ringacc 3c000000.ringacc: RA Proxy rev. 66349100, num_proxies:64
[    2.447770] printk: console [ttyS2] disabled
[    2.453511] 2880000.serial: ttyS2 at MMIO 0x2880000 (irq = 216, base_baud = 3000000) is a 8250
[    2.464844] printk: console [ttyS2] enabled
[    2.464844] printk: console [ttyS2] enabled
[    2.475460] printk: bootconsole [ns16550a0] disabled
[    2.475460] printk: bootconsole [ns16550a0] disabled
[    2.530688] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.542191] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver TI DP83867
[    2.552568] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
[    2.568760] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[    2.577779] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[    2.585692] pps pps0: new PPS source ptp0
[    2.592472] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:1
[    2.646658] davinci_mdio c200f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    2.657612] davinci_mdio c200f00.mdio: phy[0]: device c200f00.mdio:00, driver TI DP83867
[    2.667756] am65-cpsw-nuss c200000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
[    2.683763] am65-cpsw-nuss c200000.ethernet: Use random MAC address
[    2.691593] am65-cpsw-nuss c200000.ethernet: initialized cpsw ale version 1.4
[    2.700490] am65-cpsw-nuss c200000.ethernet: ALE Table size 64
[    2.709912] am65-cpsw-nuss c200000.ethernet: CPTS ver 0x4e8a010b, freq:200000000, add_val:4 pps:0
[    2.725755] am65-cpts 310d0000.cpts: CPTS ver 0x4e8a010c, freq:250000000, add_val:3 pps:0
[    2.737427] mmc0: CQHCI version 5.10
[    2.795540] mmc0: SDHCI controller on 4f80000.mmc [4f80000.mmc] using ADMA 64-bit
[    3.085706] tps6594-rtc tps6594-rtc.4.auto: registered as rtc0
[    3.093180] tps6594-rtc tps6594-rtc.4.auto: hctosys: unable to read the hardware clock
[    3.103710] omap-mailbox 31f80000.mailbox: omap mailbox rev 0x66fca100
[    3.112258] omap-mailbox 31f81000.mailbox: omap mailbox rev 0x66fca100
[    3.120765] omap-mailbox 31f82000.mailbox: omap mailbox rev 0x66fca100
[    3.129245] omap-mailbox 31f83000.mailbox: omap mailbox rev 0x66fca100
[    3.137732] omap-mailbox 31f84000.mailbox: omap mailbox rev 0x66fca100
[    3.146230] omap-mailbox 31f85000.mailbox: omap mailbox rev 0x66fca100
[    3.159120] ti-udma 285c0000.dma-controller: Channels: 22 (tchan: 11, rchan: 11, gp-rflow: 8)
[    3.171958] ti-udma 31150000.dma-controller: Channels: 66 (tchan: 33, rchan: 33, gp-rflow: 16)
[    3.187665] spi-nor spi0.0: s28hs512t (65536 Kbytes)
[    3.193977] 7 fixed-partitions partitions found on MTD device 47040000.spi.0
[    3.202776] Creating 7 MTD partitions on "47040000.spi.0":
[    3.209615] 0x000000000000-0x000000080000 : "ospi.tiboot3"
[    3.217515] 0x000000080000-0x000000280000 : "ospi.tispl"
[    3.224972] 0x000000280000-0x000000680000 : "ospi.u-boot"
[    3.232490] 0x000000680000-0x0000006c0000 : "ospi.env"
[    3.239674] 0x0000006c0000-0x000000700000 : "ospi.env.backup"
[    3.247702] 0x000000800000-0x000003fc0000 : "ospi.rootfs"
[    3.255207] 0x000003fc0000-0x000004000000 : "ospi.phypattern"
[    3.276012] spi-nor spi1.0: mt25qu512a (65536 Kbytes)
[    3.282383] 7 fixed-partitions partitions found on MTD device 47050000.spi.0
[    3.291183] Creating 7 MTD partitions on "47050000.spi.0":
[    3.298026] 0x000000000000-0x000000080000 : "qspi.tiboot3"
[    3.306013] 0x000000080000-0x000000280000 : "qspi.tispl"
[    3.313661] 0x000000280000-0x000000680000 : "qspi.u-boot"
[    3.321267] 0x000000680000-0x0000006c0000 : "qspi.env"
[    3.328619] 0x0000006c0000-0x000000700000 : "qspi.env.backup"
[    3.336653] 0x000000800000-0x000003fc0000 : "qspi.rootfs"
[    3.344225] 0x000003fc0000-0x000004000000 : "qspi.phypattern"
[    3.390685] davinci_mdio 46000f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    3.401818] davinci_mdio 46000f00.mdio: phy[0]: device 46000f00.mdio:00, driver TI DP83867
[    3.412179] am65-cpsw-nuss 46000000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
[    3.428306] am65-cpsw-nuss 46000000.ethernet: initialized cpsw ale version 1.4
[    3.437323] am65-cpsw-nuss 46000000.ethernet: ALE Table size 64
[    3.450599] pps pps0: new PPS source ptp1
[    3.459951] am65-cpsw-nuss 46000000.ethernet: CPTS ver 0x4e8a010b, freq:500000000, add_val:1 pps:1
[    3.473502] am65-cpsw-nuss 46000000.ethernet: set new flow-id-base 48
[    3.522945] davinci_mdio c200f00.mdio: davinci mdio revision 9.7, bus freq 1000000
[    3.546776] davinci_mdio c200f00.mdio: phy[0]: device c200f00.mdio:00, driver TI DP83867
[    3.557103] am65-cpsw-nuss c200000.ethernet: initializing am65 cpsw nuss version 0x6BA02102, cpsw version 0x6BA82102 Ports: 2 quirks:00000000
[    3.573393] am65-cpsw-nuss c200000.ethernet: Use random MAC address
[    3.581239] am65-cpsw-nuss c200000.ethernet: initialized cpsw ale version 1.4
[    3.590150] am65-cpsw-nuss c200000.ethernet: ALE Table size 64
[    3.608754] am65-cpsw-nuss c200000.ethernet: CPTS ver 0x4e8a010b, freq:200000000, add_val:4 pps:0
[    3.623114] am65-cpsw-nuss c200000.ethernet: set new flow-id-base 82
[    3.634981] debugfs: Directory 'pd:74' with parent 'pm_genpd' already present!
[    3.635174] mmc1: CQHCI version 5.10
[    3.644103] debugfs: Directory 'pd:73' with parent 'pm_genpd' already present!
[    3.657831] debugfs: Directory 'pd:72' with parent 'pm_genpd' already present!
[    3.667967] debugfs: Directory 'pd:335' with parent 'pm_genpd' already present!
[    3.677139] debugfs: Directory 'pd:333' with parent 'pm_genpd' already present!
[    3.686301] debugfs: Directory 'pd:332' with parent 'pm_genpd' already present!
[    3.697915] mmc1: SDHCI controller on 4fb0000.mmc [4fb0000.mmc] using ADMA 64-bit
[    3.708442] ALSA device list:
[    3.712294]   No soundcards found.
[    3.718291] Waiting for root device /dev/mmcblk1p2...

Fullscreen R5F_LOG.txt Download

SBL Revision: 01.00.10.01 (Jan 16 2024 - 19:50:17)
TIFS ver: 9.1.2--v09.01.02 (Kool Koala)
SCISERVER Board Configuration header population... PASSED
Sciclient_setBoardConfigHeader... PASSED
Initlialzing PLLs ...done.
InitlialzingClocks ...done.

Starting PBIST failure insertion test on Main Infra1 PBIST, index 3...

Starting PBIST test on Main Infra1 PBIST, index 3...

Starting PBIST failure insertion test on Main Infra0 PBIST, index 8...

Starting PBIST test on Main Infra0 PBIST, index 8...
PBIST functional test failed for 8

Starting PBIST failure insertion test on MSMC PBIST, index 26...

Starting PBIST test on MSMC PBIST, index 26...

Starting PBIST failure insertion test on NAVSS PBIST, index 7...

Starting PBIST test on NAVSS PBIST, index 7...

Starting PBIST failure insertion test on HC PBIST, index 10...

Starting PBIST test on HC PBIST, index 10...
Resetting Main Domain ...done.
Recovering Main Domain ...Unlocking pll mmrs ...done.
Unlocking CTRL MMRs ...done.
done.
Initlialzing DDR ...done.
Initializing GTC ...Copying EEPROM content to DDR ...
EEPROM Data Copy Done.
Begin parsing user application
Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
Calling Sciclient_procBootRequestProcessor, ProcId 0x21...
Calling Sciclient_procBootRequestProcessor, ProcId 0x22...
Calling Sciclient_procBootRequestProcessor, ProcId 0x23...
Calling Sciclient_procBootRequestProcessor, ProcId 0x24...
Calling Sciclient_procBootRequestProcessor, ProcId 0x25...
Calling Sciclient_procBootRequestProcessor, ProcId 0x26...
Calling Sciclient_procBootRequestProcessor, ProcId 0x27...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
Calling Sciclient_procBootRequestProcessor, ProcId 0x6...
Calling Sciclient_procBootRequestProcessor, ProcId 0x7...
Calling Sciclient_procBootRequestProcessor, ProcId 0x8...
Calling Sciclient_procBootRequestProcessor, ProcId 0x9...
Calling Sciclient_procBootRequestProcessor, ProcId 0xa...
Calling Sciclient_procBootRequestProcessor, ProcId 0xb...
Calling Sciclient_procBootRequestProcessor, ProcId 0x30...
Calling Sciclient_procBootRequestProcessor, ProcId 0x31...
Calling Sciclient_procBootRequestProcessor, ProcId 0x32...
Calling Sciclient_procBootRequestProcessor, ProcId 0x33...
Calling Sciclient_procBootRequestProcessor, ProcId 0x80...
Searching for X509 certificate ...not found
Switching core id 8, proc_id 0x1 to split mode...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Sciclient_procBootSetProcessorCfg, ProcId 0x1, enabling split mode...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Enabling MCU TCMs after reset for core 8
Disabling HW-based memory init of MCU TCMs for core 8
Sciclient_procBootSetProcessorCfg update TCM enable/disable settings...
Copying 0x40 bytes to 0x0
Copying 0x20940 bytes to 0x41c82000
Copying 0xe6a8 bytes to 0x41cbb880
Copying 0x53b0 bytes to 0x41cd1f28
Copying 0x1604 bytes to 0x41cd8a80
Copying 0x4d0 bytes to 0x41cda088
Copying 0x358 bytes to 0x41cda558
Copying 0x100 bytes to 0x41cda8b0
Copying 0x58 bytes to 0x41cda9b0
Copying 0x3718 bytes to 0x41cdaa08
Setting entry point for core 8 @0x0
Sciclient_procBootReleaseProcessor, ProcId 0x20...
Sciclient_procBootReleaseProcessor, ProcId 0x21...
Sciclient_procBootReleaseProcessor, ProcId 0x22...
Sciclient_procBootReleaseProcessor, ProcId 0x23...
Sciclient_procBootReleaseProcessor, ProcId 0x24...
Sciclient_procBootReleaseProcessor, ProcId 0x25...
Sciclient_procBootReleaseProcessor, ProcId 0x26...
Sciclient_procBootReleaseProcessor, ProcId 0x27...
Sciclient_procBootReleaseProcessor, ProcId 0x1...
Sciclient_procBootReleaseProcessor, ProcId 0x2...
Sciclient_procBootReleaseProcessor, ProcId 0x6...
Sciclient_procBootReleaseProcessor, ProcId 0x7...
Sciclient_procBootReleaseProcessor, ProcId 0x8...
Sciclient_procBootReleaseProcessor, ProcId 0x9...
Sciclient_procBootReleaseProcessor, ProcId 0xa...
Sciclient_procBootReleaseProcessor, ProcId 0xb...
Sciclient_procBootReleaseProcessor, ProcId 0x30...
Sciclient_procBootReleaseProcessor, ProcId 0x31...
Sciclient_procBootReleaseProcessor, ProcId 0x32...
Sciclient_procBootReleaseProcessor, ProcId 0x33...
Sciclient_procBootReleaseProcessor, ProcId 0x80...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Sciclient_procBootSetProcessorCfg, ProcId 0x1, EntryPoint 0x0...
Sciclient_pmSetModuleClkFreq, DevId 0x15a @ 1000000000Hz...
Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x2, EntryPoint 0xfffffffe...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Starting Sciserver..... PASSED

MCU R5F App started at 0 usecs

Starting PBIST failure insertion test on PBIST HWPOST MCU, index 0...

Starting PBIST test on PBIST HWPOST MCU, index 0...
HW POST MCU Status : SDL_PBIST_POST_COMPLETED_SUCCESS

Starting PBIST Test Of ROM on PBIST HWPOST MCU, index 0...
HW POST MCU Status : SDL_LBIST_POST_NOT_RUN
HW POST DMSC Status : SDL_LBIST_POST_NOT_RUN
HW POST MCU Status : SDL_LBIST_POST_NOT_RUN
HW POST DMSC Status : SDL_LBIST_POST_NOT_RUN

Starting PBIST failure insertion test on Main R5F 0 PBIST, index 1...

Starting PBIST failure insertion test on Codec PBIST, index 2...

Starting PBIST failure insertion test on VPAC PBIST, index 4...

Starting PBIST failure insertion test on DSS EDP PBIST, index 5...

Starting PBIST failure insertion test on DMPAC PBIST, index 6...

Starting PBIST failure insertion test on GPU PBIST, index 9...

Starting PBIST failure insertion test on VPAC_1 PBIST, index 11...

Starting PBIST failure insertion test on Main R5F 2 PBIST, index 12...

Starting PBIST failure insertion test on Codec 1 PBIST, index 13...

Starting PBIST failure insertion test on C7X_0 PBIST, index 18...

Starting PBIST failure insertion test on C7X_1 PBIST, index 19...

Starting PBIST failure insertion test on C7X_2 PBIST, index 20...

Starting PBIST failure insertion test on C7X_3 PBIST, index 21...

Starting PBIST failure insertion test on ANA_0 PBIST, index 22...

Starting PBIST failure insertion test on ANA_1 PBIST, index 23...

Starting PBIST failure insertion test on ANA_2 PBIST, index 24...

Starting PBIST failure insertion test on ANA_3 PBIST, index 25...

Starting PBIST failure insertion test on Main R5F 1 PBIST, index 27...

Starting PBIST test on Main R5F 0 PBIST, index 1...

Starting PBIST test on Codec PBIST, index 2...

Starting PBIST test on VPAC PBIST, index 4...

Starting PBIST test on DSS EDP PBIST, index 5...

Starting PBIST test on DMPAC PBIST, index 6...

Starting PBIST test on GPU PBIST, index 9...

Starting PBIST test on VPAC_1 PBIST, index 11...

Starting PBIST test on Main R5F 2 PBIST, index 12...

Starting PBIST test on Codec 1 PBIST, index 13...

Starting PBIST test on C7X_0 PBIST, index 18...

Starting PBIST test on C7X_1 PBIST, index 19...

Starting PBIST test on C7X_2 PBIST, index 20...

Starting PBIST test on C7X_3 PBIST, index 21...

Starting PBIST test on ANA_0 PBIST, index 22...

Starting PBIST test on ANA_1 PBIST, index 23...

Starting PBIST test on ANA_2 PBIST, index 24...

Starting PBIST test on ANA_3 PBIST, index 25...

Starting PBIST test on Main R5F 1 PBIST, index 27...

Starting PBIST Test Of ROM on Main R5F 0 PBIST, index 1...

Starting PBIST Test Of ROM on Codec PBIST, index 2...

Starting PBIST Test Of ROM on VPAC PBIST, index 4...

Starting PBIST Test Of ROM on DSS EDP PBIST, index 5...

Starting PBIST Test Of ROM on DMPAC PBIST, index 6...

Starting PBIST Test Of ROM on GPU PBIST, index 9...

Starting PBIST Test Of ROM on VPAC_1 PBIST, index 11...

Starting PBIST Test Of ROM on Main R5F 2 PBIST, index 12...

Starting PBIST Test Of ROM on Codec 1 PBIST, index 13...

Starting PBIST Test Of ROM on C7X_0 PBIST, index 18...

Starting PBIST Test Of ROM on C7X_1 PBIST, index 19...

Starting PBIST Test Of ROM on C7X_2 PBIST, index 20...

Starting PBIST Test Of ROM on C7X_3 PBIST, index 21...

Starting PBIST Test Of ROM on ANA_0 PBIST, index 22...

Starting PBIST Test Of ROM on ANA_1 PBIST, index 23...

Starting PBIST Test Of ROM on ANA_2 PBIST, index 24...

Starting PBIST Test Of ROM on ANA_3 PBIST, index 25...

Starting PBIST Test Of ROM on Main R5F 1 PBIST, index 27...

Starting PBIST Test Of ROM on PBIST MCU PSROM, index 28...

Starting PBIST Test Of ROM on PBIST MCU_1, index 29...

Starting PBIST Test Of ROM on PBIST MCU PULSAR, index 30...

*** Boot stage 0 is complete, cores for this stage may now be loaded ***

*** Boot stage 1 is complete, cores for this stage may now be loaded ***

*** Boot stage 2 is complete, cores for this stage may now be loaded ***

==========================
BIST: Example App Summary:
==========================
BIST: Pre-boot Stage - Ran negative PBIST ID - PBIST_HWPOST_MCU_INDEX, Result = PASS
Pre-boot stage - Ran 1 negative PBIST total sections
BIST: Pre-boot Stage - Ran ROM Test PBIST ID - PBIST_HWPOST_MCU_INDEX, Result = PASS
Pre-boot stage - Ran 1 ROM Test of PBIST total sections
BIST: Pre-boot Stage - Ran PBIST ID - PBIST_HWPOST_MCU_INDEX, Result = PASS
Pre-boot stage - Ran 1 PBIST total sections
BIST: Pre-boot Stage - Ran LBIST ID - LBIST_HWPOST_INST_SMS_INDEX, Result = LBIST_POST_COMPLETED_SUCCESS
BIST: Pre-boot Stage - Ran LBIST ID - LBIST_HWPOST_INST_MCU_INDEX, Result = LBIST_POST_COMPLETED_SUCCESS
Pre-boot stage - Ran 2 LBIST total sections
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_MAINR5F0, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_CODEC, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_MAININFRA_1, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_VPAC_0, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_DSS, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_DMPAC, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_NAVSS, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_MAININFRA_0, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_GPU, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_HC, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_VPAC_1, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_MAINR5F2, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_CODEC_1, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_A72_0_0, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_A72_0_1, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_A72_1_0, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_A72_1_1, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_C7X_0, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_C7X_1, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_C7X_2, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_C7X_3, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_ANA_0, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_ANA_1, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_ANA_2, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_ANA_3, Result = PASS
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_MSMC, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran negative PBIST ID - PBIST_INSTANCE_MAINR5F1, Result = PASS
BIST: Stage 0 - Ran 30 negative PBIST total sections
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_MAINR5F0, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_CODEC, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_MAININFRA_1, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_VPAC_0, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_DSS, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_DMPAC, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_NAVSS, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_MAININFRA_0, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_GPU, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_HC, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_VPAC_1, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_MAINR5F2, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_CODEC_1, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_A72_0_0, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_A72_0_1, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_A72_1_0, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_A72_1_1, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_C7X_0, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_C7X_1, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_C7X_2, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_C7X_3, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_ANA_0, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_ANA_1, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_ANA_2, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_ANA_3, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_MSMC, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_MAINR5F1, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_MCU_PSROM, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_MCU_1, Result = PASS
BIST: Stage 0 - Ran ROM Test PBIST ID - PBIST_INSTANCE_MCU_PULSAR, Result = PASS
BIST: Stage 0 - Ran 30 ROM Test PBIST total sections
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_MAINR5F0, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_CODEC, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_MAININFRA_1, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_VPAC_0, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_DSS, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_DMPAC, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_NAVSS, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_MAININFRA_0, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_GPU, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_HC, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_VPAC_1, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_MAINR5F2, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_CODEC_1, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_A72_0_0, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_A72_0_1, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_A72_1_0, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_A72_1_1, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_C7X_0, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_C7X_1, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_C7X_2, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_C7X_3, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_ANA_0, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_ANA_1, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_ANA_2, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_ANA_3, Result = PASS
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_MSMC, Result = FAIL or NOT RUN
BIST: Stage 0 - Ran PBIST ID - PBIST_INSTANCE_MAINR5F1, Result = PASS
BIST: Stage 0 - Ran 30 PBIST total sections
BIST: Stage 0 - Ran LBIST ID - LBIST_INST_MAINR5F0_INDEX, Result = PASS
BIST: Stage 0 - Ran LBIST ID - LBIST_INST_MAINR5F2_INDEX, Result = PASS
BIST: Stage 0 - Ran 2 LBIST sections
BIST: Stage 1 - Ran 0 negative PBIST total sections
BIST: Stage 1 - Ran 0 ROM Test PBIST total sections
BIST: Stage 1 - Ran 0 PBIST total sections
BIST: Stage 1 - Ran LBIST ID - LBIST_INST_MAINR5F1_INDEX, Result = PASS
BIST: Stage 1 - Ran LBIST ID - LBIST_INST_C7X0_INDEX, Result = PASS
BIST: Stage 1 - Ran LBIST ID - LBIST_INST_C7X1_INDEX, Result = PASS
BIST: Stage 1 - Ran LBIST ID - LBIST_INST_C7X2_INDEX, Result = PASS
BIST: Stage 1 - Ran LBIST ID - LBIST_INST_C7X3_INDEX, Result = PASS
BIST: Stage 1 - Ran LBIST ID - LBIST_INST_VPAC0_INDEX, Result = PASS
BIST: Stage 1 - Ran LBIST ID - LBIST_INST_DMPAC_INDEX, Result = PASS
BIST: Stage 1 - Ran LBIST ID - LBIST_INST_A72_0_INDEX, Result = PASS
BIST: Stage 1 - Ran LBIST ID - LBIST_INST_A72_1_INDEX, Result = PASS
BIST: Stage 1 - Ran 9 LBIST sections
BIST: Stage 2 - Ran 0 negative PBIST total sections
BIST: Stage 2 - Ran 0 ROM Test PBIST total sections
BIST: Stage 2 - Ran 0 PBIST total sections
BIST: Stage 2 - Ran LBIST ID - LBIST_INST_A72SS0_CORE0_INDEX, Result = PASS
BIST: Stage 2 - Ran LBIST ID - LBIST_INST_A72SS0_CORE1_INDEX, Result = PASS
BIST: Stage 2 - Ran LBIST ID - LBIST_INST_A72SS0_CORE2_INDEX, Result = PASS
BIST: Stage 2 - Ran LBIST ID - LBIST_INST_A72SS0_CORE3_INDEX, Result = PASS
BIST: Stage 2 - Ran LBIST ID - LBIST_INST_A72SS1_CORE0_INDEX, Result = PASS
BIST: Stage 2 - Ran LBIST ID - LBIST_INST_A72SS1_CORE1_INDEX, Result = PASS
BIST: Stage 2 - Ran LBIST ID - LBIST_INST_A72SS1_CORE2_INDEX, Result = PASS
BIST: Stage 2 - Ran LBIST ID - LBIST_INST_A72SS1_CORE3_INDEX, Result = PASS
BIST: Stage 2 - Ran 8 LBIST sections

MCU Bist Task started at 13852 usecs and finished at 510916 usecs
Loading BootImage

BootApp_MMCBootImageLate: fp 0x 0x41c12300, fileName is 0:/lateapp1
Searching for X509 certificate ...not found
Switching core id 10, proc_id 0x6 to split mode...
Calling Sciclient_procBootGetProcessorState, ProcId 0x6...
Sciclient_procBootSetProcessorCfg, ProcId 0x6, enabling split mode...
Sciclient_pmSetModuleState Off, DevId 0x153...
Calling Sciclient_procBootGetProcessorState, ProcId 0x6...
Enabling MCU TCMs after reset for core 10
Disabling HW-based memory init of MCU TCMs for core 10
Sciclient_procBootSetProcessorCfg update TCM enable/disable settings...
Setting HALT for ProcId 0x6...
Sciclient_pmSetModuleState On, DevId 0x153...
Clearing core_id 10 (lock-step) ATCM @ 0x5c00000
Clearing core_id 10 (lock-step) BTCM @ 0x5c10000
Translating coreid 10 local ATCM addr 0x0 to SoC MCU ATCM addr 0x5c00000
Copying 0x40 bytes to 0x5c00000
Translating coreid 10 local ATCM addr 0x40 to SoC MCU ATCM addr 0x5c00040
Copying 0x508 bytes to 0x5c00040
Translating coreid 10 local ATCM addr 0x548 to SoC MCU ATCM addr 0x5c00548
Copying 0x358 bytes to 0x5c00548
Translating coreid 10 local ATCM addr 0x8a0 to SoC MCU ATCM addr 0x5c008a0
Copying 0x120 bytes to 0x5c008a0
Translating coreid 10 local ATCM addr 0x9c0 to SoC MCU ATCM addr 0x5c009c0
Copying 0x58 bytes to 0x5c009c0
Copying 0x8c bytes to 0xa2100000
Copying 0x2c0 bytes to 0xa2100400
Copying 0xdf2c0 bytes to 0xa34b2000
Copying 0x44d70 bytes to 0xa36cb800
Copying 0x1e0a8 bytes to 0xa3728570
Setting entry point for core 10 @0x0
Switching core id 10, proc_id 0x6 to split mode...
Calling Sciclient_procBootGetProcessorState, ProcId 0x6...
Sciclient_procBootSetProcessorCfg, ProcId 0x6, enabling split mode...
Sciclient_pmSetModuleState Off, DevId 0x154...
Calling Sciclient_procBootGetProcessorState, ProcId 0x7...
Enabling MCU TCMs after reset for core 11
Sciclient_procBootSetProcessorCfg update TCM enable/disable settings...
Setting HALT for ProcId 0x7...
Sciclient_pmSetModuleState On, DevId 0x154...
Clearing core_id 11 (lock-step) ATCM @ 0x5d00000
Clearing core_id 11 (lock-step) BTCM @ 0x5d10000
Translating coreid 11 local ATCM addr 0x0 to SoC MCU ATCM addr 0x5d00000
Copying 0x40 bytes to 0x5d00000
Translating coreid 11 local ATCM addr 0x40 to SoC MCU ATCM addr 0x5d00040
Copying 0x508 bytes to 0x5d00040
Translating coreid 11 local ATCM addr 0x548 to SoC MCU ATCM addr 0x5d00548
Copying 0x358 bytes to 0x5d00548
Translating coreid 11 local ATCM addr 0x8a0 to SoC MCU ATCM addr 0x5d008a0
Copying 0x120 bytes to 0x5d008a0
Translating coreid 11 local ATCM addr 0x9c0 to SoC MCU ATCM addr 0x5d009c0
Copying 0x58 bytes to 0x5d009c0
Copying 0x8c bytes to 0xa4100000
Copying 0x2c0 bytes to 0xa43831fc
Copying 0x2b860 bytes to 0xa4588000
Copying 0x1ee10 bytes to 0xa45b3860
Copying 0xcc8 bytes to 0xa45f1e00
Setting entry point for core 11 @0x0

Called SBL_MulticoreImageParse, status = 0
BootImage completed, status = 0
Calling Sciclient_procBootRequestProcessor, ProcId 0x6...
Sciclient_procBootSetProcessorCfg, ProcId 0x6, EntryPoint 0x0...
Sciclient_pmSetModuleClkFreq, DevId 0x153 @ 1000000000Hz...
Clearing HALT for ProcId 0x6...
Sciclient_procBootReleaseProcessor, ProcId 0x6...
SBL_SlaveCoreBoot completed for Core ID#10, Entry point is 0x0
Calling Sciclient_procBootRequestProcessor, ProcId 0x7...
Sciclient_procBootSetProcessorCfg, ProcId 0x7, EntryPoint 0x0...
Sciclient_pmSetModuleClkFreq, DevId 0x154 @ 1000000000Hz...
Clearing HALT for ProcId 0x7...
Sciclient_procBootReleaseProcessor, ProcId 0x7...
SBL_SlaveCoreBoot completed for Core ID#11, Entry point is 0x0
Loading BootImage

BootApp_MMCBootImageLate: fp 0x 0x41c12300, fileName is 0:/lateapp2
Searching for X509 certificate ...not found
Switching core id 12, proc_id 0x8 to split mode...
Calling Sciclient_procBootGetProcessorState, ProcId 0x8...
Sciclient_procBootSetProcessorCfg, ProcId 0x8, enabling split mode...
Sciclient_pmSetModuleState Off, DevId 0x155...
Calling Sciclient_procBootGetProcessorState, ProcId 0x8...
Enabling MCU TCMs after reset for core 12
Disabling HW-based memory init of MCU TCMs for core 12
Sciclient_procBootSetProcessorCfg update TCM enable/disable settings...
Setting HALT for ProcId 0x8...
Sciclient_pmSetModuleState On, DevId 0x155...
Clearing core_id 12 (lock-step) ATCM @ 0x5e00000
Clearing core_id 12 (lock-step) BTCM @ 0x5e10000
Translating coreid 12 local ATCM addr 0x0 to SoC MCU ATCM addr 0x5e00000
Copying 0x40 bytes to 0x5e00000
Translating coreid 12 local ATCM addr 0x40 to SoC MCU ATCM addr 0x5e00040
Copying 0x508 bytes to 0x5e00040
Translating coreid 12 local ATCM addr 0x548 to SoC MCU ATCM addr 0x5e00548
Copying 0x358 bytes to 0x5e00548
Translating coreid 12 local ATCM addr 0x8a0 to SoC MCU ATCM addr 0x5e008a0
Copying 0x120 bytes to 0x5e008a0
Translating coreid 12 local ATCM addr 0x9c0 to SoC MCU ATCM addr 0x5e009c0
Copying 0x58 bytes to 0x5e009c0
Copying 0x8c bytes to 0xa5100000
Copying 0x18660 bytes to 0xa5540000
Copying 0x71d0 bytes to 0xa5570660
Copying 0x2c0 bytes to 0xa557e480
Copying 0xab8 bytes to 0xa557e740
Setting entry point for core 12 @0x0
Switching core id 12, proc_id 0x8 to split mode...
Calling Sciclient_procBootGetProcessorState, ProcId 0x8...
Sciclient_procBootSetProcessorCfg, ProcId 0x8, enabling split mode...
Sciclient_pmSetModuleState Off, DevId 0x156...
Calling Sciclient_procBootGetProcessorState, ProcId 0x9...
Enabling MCU TCMs after reset for core 13
Sciclient_procBootSetProcessorCfg update TCM enable/disable settings...
Setting HALT for ProcId 0x9...
Sciclient_pmSetModuleState On, DevId 0x156...
Clearing core_id 13 (lock-step) ATCM @ 0x5f00000
Clearing core_id 13 (lock-step) BTCM @ 0x5f10000
Translating coreid 13 local ATCM addr 0x0 to SoC MCU ATCM addr 0x5f00000
Copying 0x40 bytes to 0x5f00000
Translating coreid 13 local ATCM addr 0x40 to SoC MCU ATCM addr 0x5f00040
Copying 0x508 bytes to 0x5f00040
Translating coreid 13 local ATCM addr 0x548 to SoC MCU ATCM addr 0x5f00548
Copying 0x358 bytes to 0x5f00548
Translating coreid 13 local ATCM addr 0x8a0 to SoC MCU ATCM addr 0x5f008a0
Copying 0x120 bytes to 0x5f008a0
Translating coreid 13 local ATCM addr 0x9c0 to SoC MCU ATCM addr 0x5f009c0
Copying 0x58 bytes to 0x5f009c0
Copying 0x8c bytes to 0xa6100000
Copying 0x18660 bytes to 0xa6540000
Copying 0x71d0 bytes to 0xa6570660
Copying 0x2c0 bytes to 0xa657e480
Copying 0xab8 bytes to 0xa657e740
Setting entry point for core 13 @0x0
Switching core id 14, proc_id 0xa to split mode...
Calling Sciclient_procBootGetProcessorState, ProcId 0xa...
Sciclient_procBootSetProcessorCfg, ProcId 0xa, enabling split mode...
Sciclient_pmSetModuleState Off, DevId 0x157...
Calling Sciclient_procBootGetProcessorState, ProcId 0xa...
Enabling MCU TCMs after reset for core 14
Disabling HW-based memory init of MCU TCMs for core 14
Sciclient_procBootSetProcessorCfg update TCM enable/disable settings...
Setting HALT for ProcId 0xa...
Sciclient_pmSetModuleState On, DevId 0x157...
Clearing core_id 14 (lock-step) ATCM @ 0x5900000
Clearing core_id 14 (lock-step) BTCM @ 0x5910000
Translating coreid 14 local ATCM addr 0x0 to SoC MCU ATCM addr 0x5900000
Copying 0x40 bytes to 0x5900000
Translating coreid 14 local ATCM addr 0x40 to SoC MCU ATCM addr 0x5900040
Copying 0x508 bytes to 0x5900040
Translating coreid 14 local ATCM addr 0x548 to SoC MCU ATCM addr 0x5900548
Copying 0x358 bytes to 0x5900548
Translating coreid 14 local ATCM addr 0x8a0 to SoC MCU ATCM addr 0x59008a0
Copying 0x120 bytes to 0x59008a0
Translating coreid 14 local ATCM addr 0x9c0 to SoC MCU ATCM addr 0x59009c0
Copying 0x58 bytes to 0x59009c0
Copying 0x8c bytes to 0xa7100000
Copying 0x2c0 bytes to 0xa7100400
Copying 0x4d260 bytes to 0xa7b62000
Copying 0x1daa0 bytes to 0xa7bd0100
Copying 0x5fa0 bytes to 0xa7c05ba0
Setting entry point for core 14 @0x0
Switching core id 14, proc_id 0xa to split mode...
Calling Sciclient_procBootGetProcessorState, ProcId 0xa...
Sciclient_procBootSetProcessorCfg, ProcId 0xa, enabling split mode...
Sciclient_pmSetModuleState Off, DevId 0x158...
Calling Sciclient_procBootGetProcessorState, ProcId 0xb...
Enabling MCU TCMs after reset for core 15
Sciclient_procBootSetProcessorCfg update TCM enable/disable settings...
Setting HALT for ProcId 0xb...
Sciclient_pmSetModuleState On, DevId 0x158...
Clearing core_id 15 (lock-step) ATCM @ 0x5a00000
Clearing core_id 15 (lock-step) BTCM @ 0x5a10000
Translating coreid 15 local ATCM addr 0x0 to SoC MCU ATCM addr 0x5a00000
Copying 0x40 bytes to 0x5a00000
Translating coreid 15 local ATCM addr 0x40 to SoC MCU ATCM addr 0x5a00040
Copying 0x508 bytes to 0x5a00040
Translating coreid 15 local ATCM addr 0x548 to SoC MCU ATCM addr 0x5a00548
Copying 0x358 bytes to 0x5a00548
Translating coreid 15 local ATCM addr 0x8a0 to SoC MCU ATCM addr 0x5a008a0
Copying 0x120 bytes to 0x5a008a0
Translating coreid 15 local ATCM addr 0x9c0 to SoC MCU ATCM addr 0x5a009c0
Copying 0x58 bytes to 0x5a009c0
Copying 0x8c bytes to 0xa8100000
Copying 0x18660 bytes to 0xa8540000
Copying 0x71d0 bytes to 0xa8570660
Copying 0x2c0 bytes to 0xa857e480
Copying 0xab8 bytes to 0xa857e740
Setting entry point for core 15 @0x0
Copying 0x98 bytes to 0xb2100000
Copying 0x40 bytes to 0xb2200000
Copying 0x840 bytes to 0xb2400000
Copying 0x840 bytes to 0xb2600000
Copying 0x5e5c00 bytes to 0xb2800000
Copying 0x1000 bytes to 0xb30c40f0
Copying 0x20 bytes to 0xb30c5210
Copying 0x35470 bytes to 0xb32f0000
Copying 0x1ee4c bytes to 0xb33a0000
Setting entry point for core 18 @0xb2200000
Copying 0x98 bytes to 0xb4100000
Copying 0x40 bytes to 0xb4200000
Copying 0x840 bytes to 0xb4400000
Copying 0x840 bytes to 0xb4600000
Copying 0x630e40 bytes to 0xb4800000
Copying 0x20 bytes to 0xb4e30f60
Copying 0x35740 bytes to 0xb533a000
Copying 0x32118 bytes to 0xb536f740
Copying 0x1000 bytes to 0xb53c5008
Setting entry point for core 19 @0xb4200000
Copying 0x98 bytes to 0xb6100000
Copying 0x40 bytes to 0xb6200000
Copying 0x840 bytes to 0xb6400000
Copying 0x840 bytes to 0xb6600000
Copying 0x5d5b00 bytes to 0xb6800000
Copying 0x20 bytes to 0xb6dd5b00
Copying 0x1000 bytes to 0xb70b40f8
Copying 0x35400 bytes to 0xb72e0000
Copying 0x1e42c bytes to 0xb7380000
Setting entry point for core 20 @0xb6200000
Copying 0x98 bytes to 0xb8100000
Copying 0x40 bytes to 0xb8200000
Copying 0x840 bytes to 0xb8400000
Copying 0x840 bytes to 0xb8600000
Copying 0x5d5b00 bytes to 0xb8800000
Copying 0x20 bytes to 0xb8dd5b00
Copying 0x1000 bytes to 0xb90b40f8
Copying 0x35400 bytes to 0xb92e0000
Copying 0x1e42c bytes to 0xb9380000
Setting entry point for core 21 @0xb8200000

Called SBL_MulticoreImageParse, status = 0
BootImage completed, status = 0
Calling Sciclient_procBootRequestProcessor, ProcId 0x8...
Sciclient_procBootSetProcessorCfg, ProcId 0x8, EntryPoint 0x0...
Sciclient_pmSetModuleClkFreq, DevId 0x155 @ 1000000000Hz...
Clearing HALT for ProcId 0x8...
Sciclient_procBootReleaseProcessor, ProcId 0x8...
SBL_SlaveCoreBoot completed for Core ID#12, Entry point is 0x0
Calling Sciclient_procBootRequestProcessor, ProcId 0x9...
Sciclient_procBootSetProcessorCfg, ProcId 0x9, EntryPoint 0x0...
Sciclient_pmSetModuleClkFreq, DevId 0x156 @ 1000000000Hz...
Clearing HALT for ProcId 0x9...
Sciclient_procBootReleaseProcessor, ProcId 0x9...
SBL_SlaveCoreBoot completed for Core ID#13, Entry point is 0x0
Calling Sciclient_procBootRequestProcessor, ProcId 0xa...
Sciclient_procBootSetProcessorCfg, ProcId 0xa, EntryPoint 0x0...
Sciclient_pmSetModuleClkFreq, DevId 0x157 @ 1000000000Hz...
Clearing HALT for ProcId 0xa...
Sciclient_procBootReleaseProcessor, ProcId 0xa...
SBL_SlaveCoreBoot completed for Core ID#14, Entry point is 0x0
Calling Sciclient_procBootRequestProcessor, ProcId 0xb...
Sciclient_procBootSetProcessorCfg, ProcId 0xb, EntryPoint 0x0...
Sciclient_pmSetModuleClkFreq, DevId 0x158 @ 1000000000Hz...
Clearing HALT for ProcId 0xb...
Sciclient_procBootReleaseProcessor, ProcId 0xb...
SBL_SlaveCoreBoot completed for Core ID#15, Entry point is 0x0
Calling Sciclient_procBootRequestProcessor, ProcId 0x30...
Sciclient_procBootSetProcessorCfg, ProcId 0x30, EntryPoint 0xb2200000...
Sciclient_pmSetModuleClkFreq, DevId 0x1e @ 1000000000Hz...
Sciclient_pmSetModuleState Off, DevId 0x164...
Sciclient_pmSetModuleState Off, DevId 0x1f...
Sciclient_pmSetModuleState Off, DevId 0x1e...
Sciclient_pmSetModuleState On, DevId 0x1e...
Sciclient_procBootReleaseProcessor, ProcId 0x30...
SBL_SlaveCoreBoot completed for Core ID#18, Entry point is 0xb2200000
Calling Sciclient_procBootRequestProcessor, ProcId 0x31...
Sciclient_procBootSetProcessorCfg, ProcId 0x31, EntryPoint 0xb4200000...
Sciclient_pmSetModuleClkFreq, DevId 0x21 @ 1000000000Hz...
Sciclient_pmSetModuleState Off, DevId 0x165...
Sciclient_pmSetModuleState Off, DevId 0x22...
Sciclient_pmSetModuleState Off, DevId 0x21...
Sciclient_pmSetModuleState On, DevId 0x21...
Sciclient_procBootReleaseProcessor, ProcId 0x31...
SBL_SlaveCoreBoot completed for Core ID#19, Entry point is 0xb4200000
Calling Sciclient_procBootRequestProcessor, ProcId 0x32...
Sciclient_procBootSetProcessorCfg, ProcId 0x32, EntryPoint 0xb6200000...
Sciclient_pmSetModuleClkFreq, DevId 0x25 @ 1000000000Hz...
Sciclient_pmSetModuleState Off, DevId 0x166...
Sciclient_pmSetModuleState Off, DevId 0x26...
Sciclient_pmSetModuleState Off, DevId 0x25...
Sciclient_pmSetModuleState On, DevId 0x25...
Sciclient_procBootReleaseProcessor, ProcId 0x32...
SBL_SlaveCoreBoot completed for Core ID#20, Entry point is 0xb6200000
Calling Sciclient_procBootRequestProcessor, ProcId 0x33...
Sciclient_procBootSetProcessorCfg, ProcId 0x33, EntryPoint 0xb8200000...
Sciclient_pmSetModuleClkFreq, DevId 0x28 @ 1000000000Hz...
Sciclient_pmSetModuleState Off, DevId 0x167...
Sciclient_pmSetModuleState Off, DevId 0x29...
Sciclient_pmSetModuleState Off, DevId 0x28...
Sciclient_pmSetModuleState On, DevId 0x28...
Sciclient_procBootReleaseProcessor, ProcId 0x33...
SBL_SlaveCoreBoot completed for Core ID#21, Entry point is 0xb8200000
Loading BootImage

BootApp_MMCBootImageLate: fp 0x 0x41c12300, fileName is 0:/atf_optee.appimage
Searching for X509 certificate ...not found
Sciclient_pmSetModuleState On, DevId 0xc6...
Copying 0xace8 bytes to 0x70000000
Copying 0x74d58 bytes to 0x9e800000
Setting entry point for core 0 @0x0

Called SBL_MulticoreImageParse, status = 0

BootApp_MMCBootImageLate: fp 0x 0x41c12300, fileName is 0:/tikernelimage_linux.appimage
Searching for X509 certificate ...not found
Sciclient_pmSetModuleState On, DevId 0xc6...
Copying 0x136ca00 bytes to 0x80080000
Setting entry point for core 0 @0x0

Called SBL_MulticoreImageParse, status = 0

BootApp_MMCBootImageLate: fp 0x 0x41c12300, fileName is 0:/tidtb_linux.appimage
Searching for X509 certificate ...not found
Sciclient_pmSetModuleState On, DevId 0xc6...
Copying 0x1bcd4 bytes to 0x82000000
Setting entry point for core 0 @0x0

MCU Boot Task started at 27 usecs and finished at 1428006 usecs

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0001_2D00_bist_2D00_test_2D00_patch_2D00_from_2D00_Kip.patch

0 KB over 1 year ago in reply to Kangjia Dong

TI__Guru** 120881 points

Hi Kangjia,

The Main Domain Reset which has been added to the SBL is likely leaving the MMCSD IP Block or associated clocks in a different state, which is adversely impacting the Linux driver. As part of the recovery from the Main Domain Reset, the code will need to adjust for this.

A delta between the MMCSD block before and after reset, is required to ascertain what the delta is. It may be some time before this can be tested on my end, but it is on the list of work items.

Should there be any bandwidth available on your end, a similar debug can be done.

Regards,

0 Kangjia Dong over 1 year ago in reply to KB

TI__Intellectual 2215 points

The following patch can fix boot Linux stuck on mount rootfs.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0001_2D00_fix_2D00_boot_2D00_Linux_2D00_block_2D00_on_2D00_the_2D00_mount_2D00_rootfs.patch

0 zhisong zheng over 1 year ago in reply to Kangjia Dong

Intellectual 431 points

Hi experts:

I applied two patchs on sdk9.1 , compiled tiboot3 and app, but linux did not start successfully.

patch -p1 < /mnt/c/Users/WangTx/Downloads/0001-bist-test-patch-from-Kip.patch
patch -p1 < /mnt/c/Users/WangTx/Downloads/0001-fix-boot-Linux-block-on-the-mount-rootfs.patch
make pdk_libs -j16 BOARD=j784s4_evm;
make sbl_mmcsd_img BOARD=j784s4_evm ;
make botot_app_mmcsd_linux BOARD=j784s4_evm ;

output log:

mcu1_0:

SBL Revision: 01.00.10.01 (Jan 23 2024 - 09:20:08)
TIFS ver: 9.1.2--v09.01.02 (Kool Koala)
SCISERVER Board Configuration header population... PASSED
Sciclient_setBoardConfigHeader... PASSED
Initlialzing PLLs ...done.
InitlialzingClocks ...done.

Starting PBIST failure insertion test on Main Infra1 PBIST, index 3...

Starting PBIST test on Main Infra1 PBIST, index 3...

Starting PBIST failure insertion test on Main Infra0 PBIST, index 8...

Starting PBIST test on Main Infra0 PBIST, index 8...
PBIST functional test failed for 8

Starting PBIST failure insertion test on MSMC PBIST, index 26...

Starting PBIST test on MSMC PBIST, index 26...

Starting PBIST failure insertion test on NAVSS PBIST, index 7...

Starting PBIST test on NAVSS PBIST, index 7...

Starting PBIST failure insertion test on HC PBIST, index 10...

Starting PBIST test on HC PBIST, index 10...
Resetting Main Domain ...done.
Recovering Main Domain ...Unlocking pll mmrs ...done.
Unlocking CTRL MMRs ...done.
done.
Initlialzing DDR ...done.
Initializing GTC ...Copying EEPROM content to DDR ...
EEPROM Data Copy Done.
Begin parsing user application
Calling Sciclient_procBootRequestProcessor, ProcId 0x20...
Calling Sciclient_procBootRequestProcessor, ProcId 0x21...
Calling Sciclient_procBootRequestProcessor, ProcId 0x22...
Calling Sciclient_procBootRequestProcessor, ProcId 0x23...
Calling Sciclient_procBootRequestProcessor, ProcId 0x24...
Calling Sciclient_procBootRequestProcessor, ProcId 0x25...
Calling Sciclient_procBootRequestProcessor, ProcId 0x26...
Calling Sciclient_procBootRequestProcessor, ProcId 0x27...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
Calling Sciclient_procBootRequestProcessor, ProcId 0x6...
Calling Sciclient_procBootRequestProcessor, ProcId 0x7...
Calling Sciclient_procBootRequestProcessor, ProcId 0x8...
Calling Sciclient_procBootRequestProcessor, ProcId 0x9...
Calling Sciclient_procBootRequestProcessor, ProcId 0xa...
Calling Sciclient_procBootRequestProcessor, ProcId 0xb...
Calling Sciclient_procBootRequestProcessor, ProcId 0x30...
Calling Sciclient_procBootRequestProcessor, ProcId 0x31...
Calling Sciclient_procBootRequestProcessor, ProcId 0x32...
Calling Sciclient_procBootRequestProcessor, ProcId 0x33...
Calling Sciclient_procBootRequestProcessor, ProcId 0x80...
Searching for X509 certificate ...not found
Switching core id 8, proc_id 0x1 to split mode...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Sciclient_procBootSetProcessorCfg, ProcId 0x1, enabling split mode...
Calling Sciclient_procBootGetProcessorState, ProcId 0x1...
Enabling MCU TCMs after reset for core 8
Disabling HW-based memory init of MCU TCMs for core 8
Sciclient_procBootSetProcessorCfg update TCM enable/disable settings...
Copying 0x40 bytes to 0x0
Copying 0x20940 bytes to 0x41c82000
Copying 0xe680 bytes to 0x41cbb880
Copying 0x53b0 bytes to 0x41cd1f00
Copying 0x1604 bytes to 0x41cd8a80
Copying 0x4d0 bytes to 0x41cda088
Copying 0x358 bytes to 0x41cda558
Copying 0x100 bytes to 0x41cda8b0
Copying 0x58 bytes to 0x41cda9b0
Copying 0x3718 bytes to 0x41cdaa08
Setting entry point for core 8 @0x0
Sciclient_procBootReleaseProcessor, ProcId 0x20...
Sciclient_procBootReleaseProcessor, ProcId 0x21...
Sciclient_procBootReleaseProcessor, ProcId 0x22...
Sciclient_procBootReleaseProcessor, ProcId 0x23...
Sciclient_procBootReleaseProcessor, ProcId 0x24...
Sciclient_procBootReleaseProcessor, ProcId 0x25...
Sciclient_procBootReleaseProcessor, ProcId 0x26...
Sciclient_procBootReleaseProcessor, ProcId 0x27...
Sciclient_procBootReleaseProcessor, ProcId 0x1...
Sciclient_procBootReleaseProcessor, ProcId 0x2...
Sciclient_procBootReleaseProcessor, ProcId 0x6...
Sciclient_procBootReleaseProcessor, ProcId 0x7...
Sciclient_procBootReleaseProcessor, ProcId 0x8...
Sciclient_procBootReleaseProcessor, ProcId 0x9...
Sciclient_procBootReleaseProcessor, ProcId 0xa...
Sciclient_procBootReleaseProcessor, ProcId 0xb...
Sciclient_procBootReleaseProcessor, ProcId 0x30...
Sciclient_procBootReleaseProcessor, ProcId 0x31...
Sciclient_procBootReleaseProcessor, ProcId 0x32...
Sciclient_procBootReleaseProcessor, ProcId 0x33...
Sciclient_procBootReleaseProcessor, ProcId 0x80...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Sciclient_procBootSetProcessorCfg, ProcId 0x1, EntryPoint 0x0...
Sciclient_pmSetModuleClkFreq, DevId 0x15a @ 1000000000Hz...
Calling Sciclient_procBootRequestProcessor, ProcId 0x2...
Skipping Sciclient_procBootSetProcessorCfg for ProcId 0x2, EntryPoint 0xfffffffe...
Calling Sciclient_procBootRequestProcessor, ProcId 0x1...
Starting Sciserver..... PASSED