AM5728: TI RTOS timing benchmark for C66x on DRA7xx platform

\Hello, 

I am working with the DSP C66x core of AM5728 SOC (ti.platforms.evmDRA7XX:dsp) and need to compare TI RTOS timings in our application with reference benchmarks.

I am referring to the link below for TI RTOS timing benchmarks:

https://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/sysbios/6_76_03_01/exports/bios_6_76_03_01/packages/ti/sysbios/benchmarks/doc-files/benchmarks.html

Here, the target for RTOS benchmarks on the evmDRA7XX platform is A15 core. Since I don't see a separate row for the C66 core, would it be ok to use the timings shown for evm6670 platform which has its target as the C66 core? 

Assuming the above reference is correct, the timing reference for semaphore post with a task switch is 225 cycles which is 375ns for a 600 MHz CPU clock. However, in my application, the time taken by semaphore_post has been measured to be in the range of 3-5microseconds. This is a drastic difference and also 3-5us is a huge amount of time taken given the time criticality in my application. 

Any pointers to what could be wrong here?

Thanks,

Dimple