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AM6442: Ethernet/IP, Profinet, Simultaneous access from custom protocol

John Hentges
Prodigy 110 points

Part Number: AM6442

I have a device in production that uses a custom Ethernet packet daemon sitting on port 18767. Ethernet/IP uses port 44818.  Can they co-exist? 

Specifically, our design uses the A53 cores in Linux to handle our protocol; the Sitara AM64x Ethernet/IP uses the R5 and PRU-ICSS cores: they use different Ethernet channels, do they not?  This would mean our design would have to have multiple RJ485/Ethernet jacks, one for the Sitara IIoT protocols and one for our custom protocol?

We're trying to enable our device as an Ethernet/IP I/O adapter, not a controller or whatever, so it will just respond to explicit messages over TCP and stream I/O data over UDP as requested.  Can I just implement the parser myself inside the A53 core as a second Daemon bound to port 44818?  Is the CIS-parsing layer source available so I don't have to write that from scratch?

When is the Discrete I/O device profile sample expected to land in the SDK?

  • 0
    TI__Mastermind 28370 points

    Hi ,

    Thanks for your query.

    I will check on this and get back to you.

    Best Regards

    Ashwani

  • 0 in reply to Ashwani Goel
    TI__Mastermind 27050 points

    The Ethernet peripheral is owned by one stack which is running in one OS, in this case ICSSG with EtherNet/IP firmware owned by a freeRTOS lwIP stack on an R5. Another application in another OS (Linux) does not have a direct interface to just listen to a port on the IP stack on the R5. My suggestion is to use a proxy application on R5, use the lwIP stack and listen to the the port 18767. Send those messages over IPC to your protocol running in Linux.

      Pekka

  • 0 in reply to Pekka Varis
    Prodigy 110 points

    If I understand then the IwIP application would also have to handle IPC replies from the Linux protocol and route them to the Ethernet, including the 2MB/sec streaming ADC data.  Alternately I can port the Linux Daemon into the R5 proxy application, IFF the R5 can access the PCI Express interface:

    Can code running on the R5 access PCI Express devices?  Our DAQ is built as an FPGA-driven circuit connected via PCI Express to the Sitara

  • 0 in reply to John Hentges
    TI__Mastermind 27050 points

    Memory behind PCIe is in the global memory map (PCIE0_DAT0 from 0x068000000 to 0x06FFFFFFF, 128 MB) R5 can go and read or write to it. Or you can use a BCDMA to copy over to local memory if R5 reading a word at a time (uncached) is too slow. Or you can have the FPGA write to the AM64x memory.

    I'm assuming you run the PCIe driver on the A53, just use R5 to access once it is all set up.

      Pekka