Hi,
I would like enable caching for access to DDR. There is some information on the wiki which says that the MAR bits need to be set on C64x+
http://processors.wiki.ti.com/index.php/Enabling_64x%2B_Cache
When I try to set the MAR bit in my .cfg file like this
var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
Cache.MAR_128_159 = 0xFFFFFFFF;
the compiler complains that MAR_128_159 is not recognised, which is fair as I don't know what exactly to set.
Do I need to set the MAR bits. And if yes, how do I do it?
cheers
Chiang