AM5K2E02: Which PCIe MSI system event should I use, and which interrupt, when they have the same description?

Gregory FEnn

Part Number: AM5K2E02

Hi all

In Table 6-22 of SPRS864D, we have system events 30 (PCIE_0_INT4) and 32 (PCIE_0_INT6). But both of these are described as "PCIE MSI Interrupt". How do I choose which one to use? What's the difference?

Likewise Table 6-23 lists the CIC2 interrupts, but none of these correspond to PCIE0, so how can I work out which interrupt to use to provide a interrupt handler when a PCIE MSI event occurs? Which should I use?

thanks,

over 2 years ago

0 Shankari G over 2 years ago

TI__Mastermind 25535 points

Gregory FEnn said:
Likewise Table 6-23 lists the CIC2 interrupts, but none of these correspond to PCIE0, so how can I work out which interrupt to use to provide a interrupt handler when a PCIE MSI event occurs? Which should I use?

It has multiple PCIE MSI ( Message signalled Interrupts ) . The system event mapping number is different . For example:- 31,32,33 etc. as mentioned in the table: 6-22

Multiple events from the PCIESS are mapped to CPU subsystem in the device. For more info please visit the PCIE user guide for keystone devices. https://www.ti.com/lit/ug/sprugs6d/sprugs6d.pdf

As well, Please have a look at the PCIE MSI interrupt enable/disable functions given at : PROCESSOR-SDK-RTOS-K2E 06_03_00_106
http://software-dl.ti.com/processor-sdk-rtos/esd/K2E/latest/index_FDS.html

In CSL_device_interrupt.h

#define CSL_ARM_GIC_PCIE_0_INT0 (0x0000001A)
#define CSL_ARM_GIC_PCIE_INT0 (0x0000001A)
#define CSL_ARM_GIC_PCIE_0_INT1 (0x0000001B)
#define CSL_ARM_GIC_PCIE_INT1 (0x0000001B)
#define CSL_ARM_GIC_PCIE_0_INT2 (0x0000001C)
#define CSL_ARM_GIC_PCIE_INT2 (0x0000001C)

====

And also have a look in "pcie.c" , functions like, PCIEMsiIntrCtrl() and PCIEMsiCtrl() etc..

Other info:-

========

Quick start Guide:- [FAQ] 66AK2E05: Would you please provide a "Quick start Guide for K2E - EVM " to enable a quick product development ? - Processors forum - Processors - TI E2E support forums

Gregory FEnn said:
Likewise Table 6-23 lists the CIC2 interrupts, but none of these correspond to PCIE0, so how can I work out which interrupt to use to provide a interrupt handler when a PCIE MSI event occurs? Which should I use?

Visit this link : -

Answer : - Please visit here :- https://e2e.ti.com/support/processors-group/processors/f/processors-forum/218981/pcie-msi-interrupt-with-different-events

Extract from the above thread. "MSIn_IRQ_STATUS is being set if the CORE RECEIVES MSI interrupt. Since Core is generating the MSI interrupt to OS/RC, you can check the similar status register on the OS/RC side. "

OS - operating system

RC - Root complex.

And also Please refer this answer too:-

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/222423/mapping-c6678-pcie-msi-interrupt-to-edma-event

Extract from the above thread "...So you may have to use MSI to generate interrupt to CPU "

For AM5K2E02, Please refer to the GIC - Generic Interrupt controller of ARM AINTC...

Regards

Shankari G