Greetings,
I am working with SDK 8.6 using a new image sensor and trying to display a test pattern at 1920x1080 resolution, 8bpp. I know that the Clock and Data Lanes 0-1 need to be inverted to the Raspberry Pi connector (i.e. P is going to N, N is going to P). We were hoping to do this with the image sensor but this is proving more difficult than anticipated so we would like to invert them at the DPHY input pins instead. I see in the TRM RevB Section "12.7.1.1 DPHY_RX Feature" states the DPHY_RX module supports "Swapping of DP/DN signals within each clock/data pair (Facilitated by CSI_RX_IF controller)"
According to Section "14.9.6.2.9.1 MMR_K3_DPHY_WRAP_LANE Register" at Physical Address 0x30111000, it looks like bits 0-4 all potentially deal with polarity for the clock and lanes being used. It isn't clear to me from the field descriptions (which are all identical) what bits 4 and 2 do and if they are required to be changed for this.
It seems to me that this currently requires an adjustment to the driver file in the Linux Kernel "drivers/phy/cdns-dphy.c". I adjusted this file as follows:
diff --git a/Desktop/kernel_configs/Cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c
index 68b871111e..272e8b909c 100644
--- a/Desktop/kernel_configs/Cadence/cdns-dphy.c
+++ b/drivers/phy/cadence/cdns-dphy.c
@@ -70,6 +70,11 @@
#define DPHY_LANE DPHY_WRAP(0x0)
#define DPHY_LANE_RESET_CMN_EN BIT(23)
+#define DPHY_LANE_DATA1CLK_SWAPDPDN BIT(4)
+#define DPHY_LANE_DATA0CLK_SWAPDPDN BIT(3)
+#define DPHY_LANE_DATA1_SWAPDPDN BIT(2)
+#define DPHY_LANE_DATA0_SWAPDPDN BIT(1)
+#define DPHY_LANE_CLK_SWAPDPDN BIT(0)
#define DPHY_ISO_CL_CTRL_L DPHY_ISO(0x10)
#define DPHY_ISO_DL_CTRL_L0 DPHY_ISO(0x14)
@@ -561,7 +566,9 @@ static int cdns_dphy_rx_configure(struct cdns_dphy *dphy,
if (soc && soc->data)
soc_data = soc->data;
if (!soc || (soc_data && !soc_data->has_hw_cmn_rstb)) {
- reg = DPHY_LANE_RESET_CMN_EN;
+ // reg = DPHY_LANE_RESET_CMN_EN; // Orignial code
+ // reg = DPHY_LANE_RESET_CMN_EN | DPHY_LANE_DATA1CLK_SWAPDPDN | DPHY_LANE_DATA0CLK_SWAPDPDN | DPHY_LANE_DATA1_SWAPDPDN | DPHY_LANE_DATA0_SWAPDPDN | DPHY_LANE_CLK_SWAPDPDN;
+ reg = DPHY_LANE_RESET_CMN_EN | DPHY_LANE_DATA1_SWAPDPDN | DPHY_LANE_DATA0_SWAPDPDN | DPHY_LANE_CLK_SWAPDPDN;
writel(reg, dphy->regs + DPHY_LANE);
}
I believe I inverted the clock and data lanes doing this. I can use devmem2 tool to read the register:
root@am62axx-evm:/# devmem2 0x30111000 w /dev/mem opened. Read at address 0x30111000 (0xffffb79cd000): 0xC0800007
Unfortunately, there are more things in question with this image sensor so I can't say that this was a proper adjustment or not because I'm not able to receive the test pattern yet. Does this appear to be the correct solution or could more information be provided for the register fields and DPHY?
This seems like something ideal for a device-tree parameter perhaps for the j721e-csi2rx device section but I didn't find anything like "lane_polarity" in the device tree documentation for it or for the cdns,csi2rx device and related phy documents.
Thank you for your support,
Steve True
