AM6442: PRU-ICSS PWM for AM64XX

Part Number: TMDS64EVM

Dear TI support team,
We are developing servo motor control using R5 and PRU of TMDS64EVM.
Can I use complementary PWM with the PRU's IEP?
I would like to know how to set it up.

Please let me know if you have sample source code.

Best regards,
Kiyomasa Imaizumi

Hello Hironari-san,

Please give me the URL to the SDK page that you are talking about.

Yes, the AM64x has 4 sets of 3 positive/negative PWM pairs (i.e., 12 primary PWM outputs, and 12 complimentary PWM outputs. Reference the Technical Reference Manual (TRM) section "PRU_ICSSG PWM Module".

You can find sample PRU firmware for controlling the PWM on this e2e thread:
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1241612/am6442-pru-icss-pwm-linux-driver

Please note that example code is for a PRU core to control the PWM outputs of the PRU_ICSSG subsystem, NOT for an R5F core to control the PWM outputs of the PRU_ICSSG subsystem.

Regards,

Nick

Hello Nick,
Thank you for teaching me about it.
Please check the URL below. 
https://software-dl.ti.com/processor-sdk-linux/esd/AM65X/07_00_01_06/exports/docs/linux/Foundational_Components/PRU-ICSSG/Linux_Drivers/pru-icssg-pwm.html

Hello Hironari-san & Kiyomasa-san,

1) Confirm part number

To confirm, you are designing with an AM64x, and not an AM65x, right?

2) what is your usecase? 

Which core do you want controlling the PRU_ICSSG PWMs?

The PRU sample firmware I linked above shows the PRU cores controlling the PRU subsystem PWMs.

The AM65x Linux SDK 7.0 documentation you linked shows the Linux A53 cores controlling the PRU subsystem PWMs.

3) talking more about that Linux driver for the PRU subsystem PWMs 

The AM64x Linux SDK docs never mention that Linux PWM driver:
https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/07_03_01_006/exports/docs/devices/AM64X/index_Linux.html (early AM64x SDK, does not even have the PRU section yet)
https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/09_00_00_03/exports/docs/linux/Foundational_Components/PRU-ICSS-Linux-Drivers.html (the latest AM64x Linux SDK doc)

It looks like AM65x Linux SDK 7.3 (Linux kernel 5.4) is the last time that Linux driver is mentioned for AM65x:
https://software-dl.ti.com/processor-sdk-linux/esd/AM65X/07_03_00_07/exports/docs/linux/Foundational_Components/PRU-ICSSG/Linux_Drivers/pru-icssg-pwm.html (SDK 7.3)
https://software-dl.ti.com/processor-sdk-linux/esd/AM65X/08_00_00_04/exports/docs/linux/Foundational_Components/PRU-ICSS-Linux-Drivers.html (SDK 8.0)

I am not sure if that Linux kernel 5.4 driver ever got ported to later releases (Linux kernel 5.10 and 6.1). I can take a look if you want.

Regards,

Nick

Hello Nick.

Thank you for your reply.
1) We are developing R5F and PRU with TMDS64EVM.
2) We use bare metal, not Linux. We would like to control BLDC servo motor with R5F and PRU's PWM output.
The R5F will calculate the PWM, pass the PWM value from R5F to the PRU, and the PRU will output the PWM.

Best regards,
Kiyomasa Imaizumi

Hello Kiyomasa-san,

Understood. In that case, the PRU project I linked in the above response is the best resource I can point you to right now:
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1263772/am6442-pru-icss-pwm-for-am64xx/4785731#4785731

If you have followup questions, feel free to reply here and we can continue the discussion.

Regards,

Nick

Hello Nick.

I would like to ask you some basic information about PWM using IEP at PRU.

What does trip state mean ?
I read TRM's "6.4.10.3 PRU_ICSSG PWM Trip State Logic" but could not understand.
Please tell me in detail what the function is.
It would be even better if there is a PWM waveform related to this.

Best Regfards,

KIyomasa Imaizumi

Hello Kiyomasa-san,

Could you please read the below referenced section and help me understand if this helps

12.4.3 Enhanced Pulse Width Modulation (EPWM) Module
This chapter describes the Enhanced Pulse Width Modulation (EPWM) module in the device.
12.4.3.1

Regards,

Sreenivasa

Hello Sreenivasa.

Thank you for your reply.
I read the EPWM chapter(12.4.3).
Is trip a function that fixes the PWM output value to Hi or Lo when some kind of error occurs?

Best regards,
Kiyomasa Imaizumi

Hello Kiyomasa-san,

Thank you.

Kiyomasa Imaizumi said:

Is trip a function that fixes the PWM output value to Hi or Lo when some kind of error occurs?

On a high level, you understanding is correct.

Regards,

Sreenivasa

Hello Sreenivasa.

Thank you for your reply immediately.

May I ask about the PWM sample project as well?
e2e.ti.com/.../ICSSG_5F00_PWM.zip

This sample is running on PRU0 of ICSSG1.
IEP clock is 333MHz and the PWM cycle of CMP0 is 64kHz.
I think tm_iep0_task runs at 64kHz and changes the CMP6 duty.
CMP6 PWM output pin is J16 at TMDS64EVM.
I tried measuring J16 with an oscilloscope, and the cycle seemed to be 32kHz.
Could you see what's going on?

Best regards,
Kiyomasa Imaizumi

Hello Kiyomasa-san,

Thank you.

I will reassign the query to Nick to support.

Regards,

Sreenivasa

Hello Nick and Sreenivasa.

Thank you.

By the way, is it possible to output complementary PWM from the PRU?

Best regards,

Kiyomasa imaizumi

Hello Nick.

I carefully read the PWM sample code on PRU.
Is the concept of complementary PWM correct in the diagram below?

1. tm_iep0_task runs in CMP0 period and sets CMP6 value to 3125
2. CMP6 compare match. PWM0_B2 is a toggle, so it goes from Lo to Hi.
3. tm_iep0_task runs in CMP0 period and sets CMP6 value to 12500 (=15625-3125)
4. Compare match for CMP6. Since PWM0_B2 is a toggle, it changes from Hi to Lo.
5. tm_iep0_task runs in CMP0 period and sets CMP6 value to 3125
6. Compare match for CMP6. PWM0_B2 is a toggle, so it goes from Lo to Hi.
7. tm_iep0_task runs in CMP0 period and sets CMP6 value to 12500 (=15625-3125)
Repeat below

Best regards,

Kiyomasa Imaizumi

Hello Kiyomasa-san,

I will not be able to take a closer look at this thread until around the middle of next week. Please let me know around Tuesday whether you figured it out, or whether you need me to take a look at the code. If you still need guidance on Tuesday, I will take a look after hearing back from you.

Regards,

Nick

Hello Nick,

Thank you.

I understand that you won't be able to see this thread until Tuesday.
I wanted to check whether the above PWM sample project implements complementary PWM. Regarding the PWM sample code, there are still some unclear points about how to use PWM , so please continue to support us after Tuesday.

Also, should I make new queries for these questions?

Best regards,

Kiyomasa Imaizumi

Hello Kiyomasa-san,

I am your contact point for asking questions specifically about the PRU PWM code linked above. So if your additional questions are about that project, you should not create a new thread.

However, if you have questions about a different subject (e.g., booting the processor), then you would want to create a separate thread for that different subject.

For now, feel free to try to load and run the PRU firmware and experiment with generating different PWM signals. If you are unfamiliar with loading and running PRU code, please reference the PRU getting started labs here: https://software-dl.ti.com/processor-sdk-linux/esd/AM64X/09_00_00_03/exports/docs/common/PRU-ICSS/PRU-Getting-Started-Labs.html

or the brand new PRU Getting Started with RTOS / R5 labs.
You can clone the very latest commit of the PSSP (NOT the latest tag, those labs were added after v6.2) from here: https://git.ti.com/cgit/pru-software-support-package/pru-software-support-package/
and the RTOS labs are here: https://git.ti.com/cgit/pru-software-support-package/pru-software-support-package/tree/examples/am243x 

Regards,

Nick

Hello Nick.

Please tell me about the PRU's PWM shadow mode.
If SHADOW_EN is 1, when is the value of IEP_CMPm_REG1[31-0] CMPm_1) loaded into IEP_CMPm_REG0[31-0] CMPm_0?
Is it the period timing of CMP0?

Best regards,

Kiyomasa Imaizumi.

Hello Nick.

Please tell me about the synchronization of R5 and PRU.
In the PRU PWM sample, IEP realizes task activation at 64kHz and 40kHz.
Is it possible to generate an interrupt on the R5 side in synchronization with task activation by IEP?

I'm thinking about synchronous processing using a timer for PRU and R5.
Do you have a sample project for interrupts with timers on R5?
I didn't have a sample project below.
C:\ti\mcu_plus_sdk_am64x_09_00_00_35\examples\drivers\timer\timer_interrupt\am64x-evm\r5fss0-0_nortos

Best regards,

Kiyomasa Imaizumi

Hello Kiyomasa-san,

Following up on earlier questions

Do you still need assistance around these points, or have you figured them out?

1) understanding the basics of what the sample code is doing (questions from https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1263772/am6442-pru-icss-pwm-for-am64xx/4790909#4790909 )

2) understanding shadow mode (questions from https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1263772/am6442-pru-icss-pwm-for-am64xx/4794845#4794845 )

Synchronization between R5F and PRU

For more information about communication between the R5F and PRU, reference:
https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/09_00_00_31/exports/docs/api_guide_am64x/DRIVERS_PRU_IPC.html
https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/09_00_00_31/exports/docs/api_guide_am64x/DRIVERS_PRUICSS_PAGE.html 

Regards,

Nick

Hello Nick.

1)
I figured out them. And I was able to output a complementary PWM waveform. thank you.

2)
This is still not resolved.
TRM has the following description.
"Shadow compare value (IEP_CMPm_REG1[31-0] CMPm_1) is loaded into active register IEP_CMPm_REG0[31-0] CMPm_0 when the controller counter is configured in 32-bit Shadow mode."

Is the timing of loading from CMPm_1 to CMPm_0 the timing of the period of CMP0?
Or is it loaded from CMPm_1 to CMPm_0 at the same time as the value is written to CMPm_1?

Best regards,
Kiyomasa Imaizumi

Hello Kiyomasa,

I am going to send your thread back to Sreenivasa to comment on how the shadow registers work.

Regards,

Nick

Also FYI, more discussion around time sync methods using the time sync router (instead of direct R5F / PRU communication) is here: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1268162/am6442-pwm-sync-between-arm-and-pru/4802778#4802778