AM6422: ECC_CTRL definition questions

Hello Thomas

Thank you for the query.

I am reviewing your inputs.

Will provide my inputs or request additional inputs based on the review at the earliest.

Regards,

Sreenivasa

Hello Thomas

Thomas Yang55737 said:

1, What is the detailed meaning of ECC_RAW， how to calculate this address? I found the  ECC_RAW definition from the code in Jacinto, but need get confirmation on AM64x ECC_RAW calculuation.

Can you please confirm if the ECC_RAW is a typo and make the required updates.

Regards,

Sreenivasa

Hello Thomas

I see the below description and if you search for ecc_row i could read some additional information.

Can you please elaborate your expectation.

Regards,

Sreenivasa

I am also confused about this. CPSW's RAM has 256 data bits, divided into 8 Encoder/Decoder Data and 8 Encoder/Decoder ECC (Refer to "12.2.1.4.6.12.3 Aggregator RAM Control"), so it requires the ECC_ROW parameter to determine where to inject an error in this RAM, right?

And what if I want to inject an error in A53SS's Data Cache RAM? "6.1.3.9 A53SS Functional Safety - ECC Error Injection Support" doesn't support any word of ECC_ROW, does this mean that ECC_ROW is not needed to be initialized in this case?

For example, A53 L2 Data RAM 0 have 72 data bits (63:0 – Data; 71:64 – ECC). If I want to flip bit 8, does it mean I need select vector 16 of register ecc_aggr_corepac_regs, then transfer 8u to ECC_BIT_1 and 0u to ECC_ROW?

Hello lina zhang

Thank you for adding your queries.

Would you mind adding this in a separate thread and updating the title for me to review or reassign.

Regards,

Sreenivasa

Added a related question AM6422: how to implement A53 data cache self-test - Processors forum - Processors - TI E2E support forums

Hello lina zhang

Thank you.

Based on the query, the thread will be assigned to an expert to support.

Regards,

Sreenivasa

Hi  Sreenivasa

Yes, I read this, ECC_ROW is applied to all RAM for ECC address search OR ONLY applied from CPSW RAM, because the above details info only exists in CPSW chapter?

-Thomas

Hello Thomas, 

Thank you 

I need you to elaborate if there is a question. You could follow the other thread if your question is similar.

Regards,

Sreenivasa

Hi  Sreenivasa,

The question is simple:

Is ECC_ROW applied to all RAM for ECC address search?

OR

Is it only applied to CPSW RAM, because the above details info only exists in CPSW chapter?

-Thomas

Hello Thomas, 

Thank you.

Let me assign the query to our safety expert.

Regards,

Sreenivasa

Hi Sreenivasa

Any update?

Thomas

Hi Sreenivasa

After more study, we know that ECC_ROW is applied to all ECC RAM for address search, but the definition need to be accurately explained. 

-Thomas

Hi  Neelima,

Could you support this? 

Thanks

Thomas

Sreenivasa,

Can you assign this to the SDL team - Vishwanath Reddy? I think this is more from the perspective of SDL api usage.

Thanks,

Neelima

Thomas Yang55737 said:

we know that ECC_ROW is applied to all ECC RAM for address search, but the definition need to be accurately explained.

This bit field is in the control and status registers of all TI IP ECC memories in the ECC wrapper / ECC aggregator. ecc_row is the protected word address (see 12.6.4.4.6 ECC_ERR_CTRL1 Register (Offset = 18h) [reset = 0h] in the TRM) in the ECC wrapper/ aggregator in the subsystem, so ecc_bit1 (12.6.4.4.7 ECC_ERR_CTRL2 Register (Offset = 1Ch) [reset = 0h]) is the one bit in the 16-bit word to flip at the address within the subsystem. ecc_bit2 is the second bit to flip.

Additionally, please see this ticket and the response posted here for more details : https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1264967/am6422-how-to-implement-a53-data-cache-self-test

Regards,

Neelima