TMDS64GPEVM: PHY ADIN1200 support

Hi,

I am not able to see anything other than the PHY addresses between eth0 and eth1 seem reversed. Could you please post the CPSW DTS node?

Best Regards,

Schuyler

Hi Schuyler

Thanks for response. Surem I will post dts nodes below:

&cpsw3g {
	pinctrl-names = "default";
	pinctrl-0 = <&cpsw_mdio0_pins_default
		     &rgmii1_io_bus_pins_default
		     &rgmii2_service_pins_default
	>;

	cpts@3d000 {
		ti,pps = <7 1>;
	};
};

&cpsw_port1 {
	status = "okay";
	phy-mode = "rgmii-rxid";
	phy-handle = <&cpsw3g_phy2>;
};

&cpsw_port2 {
	status = "okay";
	phy-mode = "rgmii-rxid";
	phy-handle = <&cpsw3g_phy1>;
};


&icssg0_mdio {

	pinctrl-names = "default";
	pinctrl-0 = <&pru_icssg0_mdio0_pins_default>;

	icssg0_phy3: ethernet-phy@3 {
                reg = <3>;
		adi,rx-internal-delay-ps = <2000>;
		adi,tx-internal-delay-ps = <2000>;
		adi,fifo-depth-bits = <8>;
        };

	icssg0_phy4: ethernet-phy@4 {  
                reg = <4>;
		adi,rx-internal-delay-ps = <2000>;
		adi,tx-internal-delay-ps = <2000>;
		adi,fifo-depth-bits = <8>;
        };
};



&cpsw3g_mdio {
	cpsw3g_phy1: ethernet-phy@1 {
		reg = <1>;
		adi,rx-internal-delay-ps = <2000>;
		adi,tx-internal-delay-ps = <2000>;
		adi,fifo-depth-bits = <8>;
		
	};

	cpsw3g_phy2: ethernet-phy@2 {
		reg = <2>;
		adi,rx-internal-delay-ps = <2000>;
		adi,tx-internal-delay-ps = <2000>;
		adi,fifo-depth-bits = <8>;
	};
};

Hi, 

You should see a link independent of any driver support if a cable with a link partner is attached.  Is the link led (assuming you are using a connector that has one) active on a connector that has a cable plugged into it?

Are you familiar with mii tools in u-boot? You should be able to read the MII registers for the PHY, please verify if the PHY is reporting auto-neg is set correctly.

Best Regards,

Schuyler

Hi Schuyler

I managed to solve this issue. It appears that there was some hardware problem that caused keeping all PHYs under reset state. Above device tree configuration is correct.

BR

Jakub

Hello

I have one more issue with this phy. I noticed that one of the PRU icssg interfaces does not work: it does not get ip address from dhcp, even setting it manually and then pinging remote side return "Destination Host Unreachable".

This logs popup when I connecting cable to eth3:

[ 304.444352] remoteproc remoteproc3: powering up 30038000.pru
[ 304.447180] remoteproc remoteproc3: Booting fw image ti-pruss/am65x-sr2-pru1-prueth-fw.elf, size 38496
root@puma:~# [ 304.447222] remoteproc remoteproc3: unsupported resource 5
[ 304.447251] remoteproc remoteproc3: remote processor 30038000.pru is now up
[ 304.447299] remoteproc remoteproc4: powering up 30006000.rtu
[ 304.461394] remoteproc remoteproc4: Booting fw image ti-pruss/am65x-sr2-rtu1-prueth-fw.elf, size 30104
[ 304.461452] remoteproc remoteproc4: remote processor 30006000.rtu is now up
[ 304.461496] remoteproc remoteproc5: powering up 3000c000.txpru
[ 304.463931] remoteproc remoteproc5: Booting fw image ti-pruss/am65x-sr2-txpru1-prueth-fw.elf, size 35836
[ 304.463992] remoteproc remoteproc5: remote processor 3000c000.txpru is now up
[ 304.480937] net eth3: started
[ 307.560051] icssg-prueth icssg0-eth eth3: Link is Up - 100Mbps/Full - flow control off
[ 307.659235] IPv6: ADDRCONF(NETDEV_CHANGE): eth3: link becomes ready
[ 304.447180] remoteproc remoteproc3: Booting fw image ti-pruss/am65x-sr2-pru1-prueth-fw.elf, size 38496

I'm wondering what does exactly mean this "unsupported resource 5". Have you any idea?

ethtool eth3 shows:

root@puma:~# ethtool eth3
Settings for eth3:
Supported ports: [ TP MII ]
Supported link modes: 10baseT/Full
100baseT/Full
Supported pause frame use: No
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT/Full
100baseT/Full
Advertised pause frame use: No
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Link partner advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
Link partner advertised pause frame use: Symmetric Receive-only
Link partner advertised auto-negotiation: Yes
Link partner advertised FEC modes: Not reported
Speed: 100Mb/s
Duplex: Full
Auto-negotiation: on
Port: Twisted Pair
PHYAD: 4
Transceiver: external
MDI-X: off (auto)
Current message level: 0x00007fff (32767)
drv probe link timer ifdown ifup rx_err tx_err tx_queued intr tx_done rx_status pktdata hw wol
Link detected: yes

And this log is constantly printed every few seconds:

[ 196.203899] am65-cpsw-nuss 8000000.ethernet eth3: txq:0 DRV_XOFF:0 tmo:41148 dql_avail:-90 free_desc:515
[ 202.091886] am65-cpsw-nuss 8000000.ethernet eth3: txq:0 DRV_XOFF:0 tmo:47036 dql_avail:-90 free_desc:515
[ 207.211894] am65-cpsw-nuss 8000000.ethernet eth3: txq:0 DRV_XOFF:0 tmo:52156 dql_avail:-90 free_desc:515
[ 213.099876] am65-cpsw-nuss 8000000.ethernet eth3: txq:0 DRV_XOFF:0 tmo:58044 dql_avail:-90 free_desc:515
[ 217.964034] am65-cpsw-nuss 8000000.ethernet eth3: txq:0 DRV_XOFF:0 tmo:62908 dql_avail:-90 free_desc:515
[ 223.083867] am65-cpsw-nuss 8000000.ethernet eth3: txq:0 DRV_XOFF:0 tmo:68028 dql_avail:-90 free_desc:515

Hi Jakub,

I have been out of the office for the last few days. I will look into the CPSW message. I do not support the PRU ICSSG but I will ask about the message.

Best Regards,

Schuyler

Hi Schuyler

Thanks for response. Below I posted entire device tree:

// SPDX-License-Identifier: GPL-2.0


/dts-v1/;

#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "../ti/k3-am642.dtsi"
#include "dt-bindings/input/linux-event-codes.h"

/ {
	compatible =  "abb,puma";
        model = "ABB Puma device";

	chosen {
		stdout-path = "serial2:115200n8";
		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
	};

    /*The unit-address must match the first address specified in the reg property of the node. */
    memory@800000000 {
		device_type = "memory";
		/* 2G RAM */
		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		secure_ddr: optee@9e800000 {
			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
			alignment = <0x1000>;
			no-map;
		};

		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa0100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa1000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa1100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa2000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa2100000 0x00 0xf00000>;
			no-map;
		};

		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa3000000 0x00 0x100000>;
			no-map;
		};

		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa3100000 0x00 0xf00000>;
			no-map;
		};

		mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa4000000 0x00 0x100000>;
			no-map;
		};

		mcu_m4fss_memory_region: m4f-memory@a4100000 {
			compatible = "shared-dma-pool";
			reg = <0x00 0xa4100000 0x00 0xf00000>;
			no-map;
		};

		rtos_ipc_memory_region: ipc-memories@a5000000 {
			reg = <0x00 0xa5000000 0x00 0x00800000>;
			alignment = <0x1000>;
			no-map;
		};
	};


	power_supplies_12v: fixed-regulator-12v0 {
		/* main DC jack */
		compatible = "regulator-fixed";
		regulator-name = "power_supplies_12v";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
	};


	
	vdd_3v3: fixed-regulator-3v3 {
                compatible = "regulator-fixed";
                regulator-name = "vdd_mmc_3v3";
                regulator-min-microvolt = <3300000>;
                regulator-max-microvolt = <3300000>;
                regulator-boot-on;
		regulator-always-on;
		vin-supply = <&power_supplies_12v>;
        };

	vdd_1v8: fixed-regulator-1v8 {
                compatible = "regulator-fixed";
                regulator-name = "vdd_mmc_1v8";
                regulator-min-microvolt = <1800000>;
                regulator-max-microvolt = <1800000>;
                regulator-boot-on;
                regulator-always-on;
                vin-supply = <&power_supplies_12v>;
        };


	leds {
		
		compatible = "gpio-leds";

		led-1 {
			label = "Status LED,BI1";
			default-state = "off";
			function = LED_FUNCTION_STATUS;
			gpios = <&status_exp2 0 GPIO_ACTIVE_LOW>; /* LED0 */
		};

		led-2 {
			label = "Status LED,BI2";
			default-state = "off";
			function = LED_FUNCTION_STATUS;
			gpios = <&status_exp2 1 GPIO_ACTIVE_LOW>; /* LED0 */
		};
		
		led-3 {
			label = "Status LED,BI3";
			default-state = "off";
			function = LED_FUNCTION_STATUS;
			gpios = <&status_exp2 2 GPIO_ACTIVE_LOW>; /* LED0 */
		};

		led-4 {
			label = "Status LED,BI4";
			default-state = "off";
			function = LED_FUNCTION_STATUS;
			gpios = <&status_exp2 3 GPIO_ACTIVE_LOW>; /* LED0 */
		};

		led-5 {
			label = "Status LED,BI5";
			default-state = "off";
			function = LED_FUNCTION_STATUS;
			gpios = <&status_exp2 4 GPIO_ACTIVE_LOW>; /* LED0 */
		};

		led-6 {
			label = "Status LED,BI6";
			default-state = "off";
			function = LED_FUNCTION_STATUS;
			gpios = <&status_exp2 5 GPIO_ACTIVE_LOW>; /* LED0 */
		};

		led-7 {
			label = "Status LED,BO1";
			default-state = "off";
			function = LED_FUNCTION_STATUS;
			gpios = <&status_exp2 6 GPIO_ACTIVE_LOW>; /* LED0 */
		};

		led-8 {
			label = "Status LED,BO2";
			default-state = "off";
			function = LED_FUNCTION_STATUS;
			gpios = <&status_exp2 7 GPIO_ACTIVE_LOW>; /* LED0 */
		};

		led-9 {
			label = "Status LED,BO3";
			default-state = "off";
			function = LED_FUNCTION_STATUS;
			gpios = <&status_exp2 8 GPIO_ACTIVE_LOW>; /* LED0 */
		};
	};


	icssg0_eth: icssg0-eth {
                compatible = "ti,am642-icssg-prueth";
                pinctrl-names = "default";
                pinctrl-0 = <&rgmii3_pru0_pins_default &rgmii4_pru1_pins_default>;

                sram = <&oc_sram>;
                ti,prus = <&pru0_0>, <&rtu0_0>, <&tx_pru0_0>, <&pru0_1>, <&rtu0_1>, <&tx_pru0_1>;
                firmware-name = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf",
                                "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf",
                                "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf",
                                "ti-pruss/am65x-sr2-pru1-prueth-fw.elf",
                                "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf",
                                "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf";

                ti,pruss-gp-mux-sel = <2>,      /* MII mode */
                                      <2>,
                                      <2>,
                                      <2>,      /* MII mode */
                                      <2>,
                                      <2>;

                mii-g-rt = <&icssg0_mii_g_rt>;
                mii-rt = <&icssg0_mii_rt>;
                iep = <&icssg0_iep0>,  <&icssg0_iep1>;

                interrupt-parent = <&icssg0_intc>;
                interrupts = <24 0 2>, <25 1 3>;
                interrupt-names = "tx_ts0", "tx_ts1";

                dmas = <&main_pktdma 0xc100 15>, /* egress slice 0 */
                       <&main_pktdma 0xc101 15>, /* egress slice 0 */
                       <&main_pktdma 0xc102 15>, /* egress slice 0 */
                       <&main_pktdma 0xc103 15>, /* egress slice 0 */
                       <&main_pktdma 0xc104 15>, /* egress slice 1 */
                       <&main_pktdma 0xc105 15>, /* egress slice 1 */
                       <&main_pktdma 0xc106 15>, /* egress slice 1 */
                       <&main_pktdma 0xc107 15>, /* egress slice 1 */
                       <&main_pktdma 0x4100 15>, /* ingress slice 0 */
		       <&main_pktdma 0x4101 15>, /* ingress slice 1 */
                       <&main_pktdma 0x4102 0>, /* mgmnt rsp slice 0 */
                       <&main_pktdma 0x4103 0>; /* mgmnt rsp slice 1 */
                dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
                            "tx1-0", "tx1-1", "tx1-2", "tx1-3",
                            "rx0", "rx1",
                            "rxmgm0", "rxmgm1";

                icssg0_emac0: ethernet-mii0 {
                        phy-handle = <&icssg0_phy3>;
                        phy-mode = "rgmii-rxid";
                        syscon-rgmii-delay = <&main_conf 0x4100>;
                        /* Filled in by bootloader */
                        local-mac-address = [00 00 00 00 00 00];
                        status = "okay";
                };

                icssg0_emac1: ethernet-mii1 {
                        phy-handle = <&icssg0_phy4>;
                        phy-mode = "rgmii-rxid";
                        syscon-rgmii-delay = <&main_conf 0x4104>;
                        /* Filled in by bootloader */
                        local-mac-address = [00 00 00 00 00 00];
                        status = "okay";
                };
        };

	};

&main_pmx0 {

	pinctrl-names = "default";
	pinctrl-0 = <&gpio_test_hardware_pins>;
	

	r5_irq_pin_default: bio-irq-pin-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x00B0, PIN_INPUT_PULLUP, 7) /* (P19) GPIO0_43 */ /* Due to the lack of external pullup resistor on the open-drain RTC CLKOUT pin, this IO need to be pulled up. */
		>;
	};

	act_relay: act-relay-pin-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x008C, PIN_OUTPUT, 7) /* (T21) GPIO0_34 */
		>;
	};

	icssg1_iep0_pins_default: icssg1-iep0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0104, PIN_OUTPUT, 2) /* (W7) PRG1_PRU0_GPO19.PRG1_IEP0_EDC_SYNC_OUT0 */
		>;
	};
	
	icssg0_iep0_pins_default: icssg0-iep0-pins-default {
                pinctrl-single,pins = <
			AM64X_IOPAD(0x01AC, PIN_OUTPUT, 2) /* (W1) PRG0_PRU0_GPO19.PRG0_IEP0_EDC_SYNC_OUT0 */
                >;
        };

	main_mmc1_pins_default: main-mmc1-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
			AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
			AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
			AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
			AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
			AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
		>;
	};

	main_gpio1_mmc_cd_pin: main-gpio1-mmc-cd-pin {
		pinctrl-single,pins = <AM64X_IOPAD(0x0298, PIN_INPUT, 7)>;
	};

	/* NAND FLASH MMC pins are configured by default */


	main_uart0_pins_default: main-uart0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
			AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
			AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
			AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
		>;
	};

	main_usb0_pins_default: main-usb0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
		>;
	};

	main_i2c1_pins_default: main-i2c1-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
			AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
		>;
	};
	
	main_i2c0_pins_default: main-i2c0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
			AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */

		>;

	};

	cpsw_mdio0_pins_default: mdio0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x015C, PIN_OUTPUT, 4) /* (Y6) PRG1_PRU0_GPIO086.MDIO0_MDC */
			AM64X_IOPAD(0x0158, PIN_INPUT, 4) /* (AA6) PRG1_PRU0_GPIO085.MDIO0_MDIO */
		>;
	};


	pru_icssg0_mdio0_pins_default: icssg0-mdio0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0204, PIN_OUTPUT, 0) /* (P3) PRG0_MDIO0_MDC */
			AM64X_IOPAD(0x0200, PIN_INPUT, 0) /* (P2) PRG0_MDIO0_MDIO */
		>;
	};

	
	rgmii3_pru0_pins_default: rgmii3-pru0-pins-default {
                pinctrl-single,pins = <
			 AM64X_IOPAD(0x0160, PIN_INPUT, 2) /* (Y1) PRG0_PRU0_GPO0.RGMII1_RD0 */
			 AM64X_IOPAD(0x0164, PIN_INPUT, 2) /* (R4) PRG0_PRU0_GPO1.RGMII1_RD1 */
			 AM64X_IOPAD(0x0168, PIN_INPUT, 2) /* (U2) PRG0_PRU0_GPO2.RGMII1_RD2 */
			 AM64X_IOPAD(0x016C, PIN_INPUT, 2) /* (V2) PRG0_PRU0_GPO3.RGMII1_RD3 */
			 AM64X_IOPAD(0x0170, PIN_INPUT, 2) /* (AA2) PRG0_PRU0_GPO4.RGMII1_RX_CTL */
			 AM64X_IOPAD(0x0178, PIN_INPUT, 2) /* (T3) PRG0_PRU0_GPO6.RGMII1_RXC */
			 AM64X_IOPAD(0x018C, PIN_OUTPUT, 2) /* (Y3) PRG0_PRU0_GPO11.RGMII1_TD0 */
			 AM64X_IOPAD(0x0190, PIN_OUTPUT, 2) /* (AA3) PRG0_PRU0_GPO12.RGMII1_TD1 */
			 AM64X_IOPAD(0x0194, PIN_OUTPUT, 2) /* (R6) PRG0_PRU0_GPO13.RGMII1_TD2 */
			 AM64X_IOPAD(0x0198, PIN_OUTPUT, 2) /* (V4) PRG0_PRU0_GPO14.RGMII1_TD3 */
			 AM64X_IOPAD(0x019C, PIN_OUTPUT, 2) /* (T5) PRG0_PRU0_GPO15.RGMII1_TX_CTL */
			 AM64X_IOPAD(0x01A0, PIN_OUTPUT, 2) /* (U4) PRG0_PRU0_GPO16.RGMII1_TXC */

                >;
        };

	rgmii4_pru1_pins_default: rgmii4-pru1-pins-default {
                pinctrl-single,pins = <
			 AM64X_IOPAD(0x01B0, PIN_INPUT, 2) /* (Y2) PRG0_PRU1_GPO0.RGMII2_RD0 */
			 AM64X_IOPAD(0x01B4, PIN_INPUT, 2) /* (W2) PRG0_PRU1_GPO1.RGMII2_RD1 */
			 AM64X_IOPAD(0x01B8, PIN_INPUT, 2) /* (V3) PRG0_PRU1_GPO2.RGMII2_RD2 */
			 AM64X_IOPAD(0x01BC, PIN_INPUT, 2) /* (T4) PRG0_PRU1_GPO3.RGMII2_RD3 */
			 AM64X_IOPAD(0x01C0, PIN_INPUT, 2) /* (W3) PRG0_PRU1_GPO4.RGMII2_RX_CTL */
			 AM64X_IOPAD(0x01C8, PIN_INPUT, 2) /* (R5) PRG0_PRU1_GPO6.RGMII2_RXC */
			 AM64X_IOPAD(0x01DC, PIN_OUTPUT, 2) /* (W4) PRG0_PRU1_GPO11.RGMII2_TD0 */
			 AM64X_IOPAD(0x01E0, PIN_OUTPUT, 2) /* (Y4) PRG0_PRU1_GPO12.RGMII2_TD1 */
			 AM64X_IOPAD(0x01E4, PIN_OUTPUT, 2) /* (T6) PRG0_PRU1_GPO13.RGMII2_TD2 */
			 AM64X_IOPAD(0x01E8, PIN_OUTPUT, 2) /* (U6) PRG0_PRU1_GPO14.RGMII2_TD3 */
			 AM64X_IOPAD(0x01EC, PIN_OUTPUT, 2) /* (U5) PRG0_PRU1_GPO15.RGMII2_TX_CTL */
			 AM64X_IOPAD(0x01F0, PIN_OUTPUT, 2) /* (AA4) PRG0_PRU1_GPO16.RGMII2_TXC */
		>;
	};


	rgmii1_io_bus_pins_default: rgmii1-io-bus-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
			AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
			AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
			AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
			AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
			AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
			AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
			AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
			AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
			AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
			AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
			AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
		>;
	};

       rgmii2_service_pins_default: rgmii2-service-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
			AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
			AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
			AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
			AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
			AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
			AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
			AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
			AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
			AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
			AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
			AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
		>;
	};

	
#if 0
	ospi0_pins_default: ospi0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
			AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
			AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
			AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
			AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
			AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
			AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
			AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
			AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
			AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
			AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
		>;
	};
#endif

	main_ecap0_pins_default: main-ecap0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
		>;
	};


	main_spi1_pins_default: main-spi1-pins-default {
                pinctrl-single,pins = <
                        AM64X_IOPAD(0x0224, PIN_INPUT, 0) /* (C14) SPI1_CLK */
                        AM64X_IOPAD(0x021C, PIN_OUTPUT, 0) /* (B14) SPI1_CS0 */
			AM64X_IOPAD(0x0220, PIN_OUTPUT, 0) /* (D14) SPI1_CS1 */
                        AM64X_IOPAD(0x0228, PIN_OUTPUT_PULLDOWN, 0) /* (B15) SPI1_D0 MOSI */
                        AM64X_IOPAD(0x022C, PIN_INPUT_PULLDOWN, 0) /* (A15) SPI1_D1 MISO */
                >;
        };
	
	main_spi0_pins_default: main-spi0-pins-default {
                pinctrl-single,pins = <
                        AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
                        AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
                        AM64X_IOPAD(0x020C, PIN_OUTPUT, 0) /* (C13) SPI0_CS1 */
                        /* uncomment these two pins configuration below when ti,pindir-d0-out-d1-in property is disabled */
                        /*AM64X_IOPAD(0x0214, PIN_INPUT_PULLDOWN, 0)*/ /* (A13) SPI0_D0 */
                        /*AM64X_IOPAD(0x0218, PIN_OUTPUT_PULLDOWN, 0)*/ /* (A14) SPI0_D1 */
                        /* uncomment these two pins configuration below when ti,pindir-d0-out-d1-in property is enabled */
                        AM64X_IOPAD(0x0214, PIN_OUTPUT_PULLDOWN, 0) /* (A13) SPI0_D0 */
                        AM64X_IOPAD(0x0218, PIN_INPUT_PULLDOWN, 0) /* (A14) SPI0_D1 */
                >;
        };


        /* if you want manipulate gpio from userspace using e.g gpiochip add desired pin to bellow node */
        gpio_test_hardware_pins: gpio-test-hardware-pins-default {
                pinctrl-single,pins = <
                        AM64X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (W19) GPIO0_37 */
                        AM64X_IOPAD(0x0008, PIN_OUTPUT, 7) /* (N19) GPIO0_2 */
                        AM64X_IOPAD(0x000C, PIN_OUTPUT, 7) /* (M19) GPIO0_3 */
                        AM64X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (E14) GPIO1_57 */
                        AM64X_IOPAD(0x0240, PIN_OUTPUT, 7) /* (E15) GPIO1_56 */
						AM64X_IOPAD(0x01FC, PIN_OUTPUT, 7) /* (R2) GPIO1_39 */
                        AM64X_IOPAD(0x00B8, PIN_OUTPUT, 7) /* (Y7) GPIO0_45 */
                        AM64X_IOPAD(0x00BC, PIN_OUTPUT, 7) /* (U8) GPIO0_46 */
						AM64X_IOPAD(0x00C0, PIN_OUTPUT, 7) /* (W8) GPIO0_47 */
						AM64X_IOPAD(0x0020, PIN_OUTPUT, 7) /* (P20) GPIO0_8 */
                 >;
        };	

};


&mcu_uart0 {
	status = "disabled";
};

&mcu_uart1 {
	status = "disabled";
};

&main_uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart0_pins_default>;
};

&main_uart1 {
	/* main_uart1 is reserved for firmware usage */
	status = "reserved";
};

&main_uart2 {
	status = "disabled";
};

&main_uart3 {
	status = "disabled";
};

&main_uart4 {
	status = "disabled";
};

&main_uart5 {
	status = "disabled";
};

&main_uart6 {
	status = "disabled";
};

&mcu_i2c0 {
	status = "disabled";

};

&mcu_i2c1 {
	status = "disabled";
};


//I2C_IO_cards
&main_i2c1 {
	status = "okay";
	pinctrl-names = "default";
        pinctrl-0 = <&main_i2c1_pins_default>;
        clock-frequency = <100000>;

	//PIO schematic (status relays expander)
	relay_exp: gpio3@75 {
		status = "okay";
		compatible = "ti,tca9539";
		reg = <0x75>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names = "EEPROM_WC","RELAY_1_EN","RELAY_1_CTRL","RELAY_1_FB",
                          "RELAY_2_EN","RELAY_2_CTRL","RELAY_2_FB",
			              "RELAY_3_EN","RELAY_3_CTRL","RELAY_3_FB",
                          "RELAY_4_EN","RELAY_4_CTRL","RELAY_4_FB",
			              "P15","P16","P17";

		interrupt-controller;
		interrupt-parent = <&main_gpio0>;
		#interrupt-cells = <2>;
		interrupts = <37 IRQ_TYPE_LEVEL_LOW>; //BIO_INT1	//@TOCHANGE

		vcc-supply = <&vdd_3v3>;
	};

	//PIO schematic (status relays expander)
	bio_exp: gpio4@76 {
		status = "okay";
		compatible = "ti,tca9539";
		reg = <0x76>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names = "EEPROM_WC","RELAY_1_EN","RELAY_1_CTRL","RELAY_1_FB",
                          "RELAY_2_EN","RELAY_2_CTRL","RELAY_2_FB",
			  "RELAY_3_EN","RELAY_3_CTRL","RELAY_3_FB",
                          "RELAY_4_EN","RELAY_4_CTRL","RELAY_4_FB",
			              "P15","P16","P17";

		interrupt-controller;
		interrupt-parent = <&main_gpio0>;
		#interrupt-cells = <2>;
		interrupts = <14 IRQ_TYPE_LEVEL_LOW>; //BIO_INT3	//@TOCHANGE

		vcc-supply = <&vdd_3v3>;
	};

	//this gpio expander is managed by R5 core
	pga_exp: gpio5@74 {
		status = "disabled";
		compatible = "ti,tca9539";
		reg = <0x74>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names = "PGA_G0","PGA_G1","PGA_G2","PGA_G4",
                            "LPCT_ENA","ALERT_ADC","UNDV",
                            "EEPROM_WC","IO_PGA_G0","IO_PGA_G1",
                            "IO_PGA_G2","IO_PGA_G3","IO_PGA_G4",
                            "IO_LPCT_ENA","P15","P16","P17";

		vcc-supply = <&vdd_3v3>;
	};

	eeprom1: eeprom1@52 {
		compatible = "st,24c04", "atmel,24c04";
		status = "okay";
		reg = <0x52>;
		pagesize = <16>; 
		size = <512>;  /* total eeprom size */
		no-read-rollover;
		address-width = <8>;
		wp-gpios = <&bio_exp 0 GPIO_ACTIVE_LOW>;
		vcc-supply = <&vdd_3v3>;
	};
	
	//expander pga_exp is putted under R5 core control so below eeprom node should not be managed by kernel
	eeprom2: eeprom2@50 {
		compatible = "st,24c04", "atmel,24c04";
		status = "disabled";
		reg = <0x50>;
		pagesize = <16>;
		size = <512>; /*·total·eeprom·size·*/
		no-read-rollover;
		address-width = <8>;
		wp-gpios = <&pga_exp 7 GPIO_ACTIVE_LOW>;
		vcc-supply = <&vdd_3v3>;
	};

	i2c_spi_converter: sc18is602b@2f {

		/* NOTE: This driver is designated for sc18is606 device
		   but it mostly compatible with sc18is602b device!

		   sc18is602b is visible in a system as new spi bus.
		   New SPI slave devices can be attached to this bus by defining
		   subnodes of sc18is602b node.
		*/

		compatible = "nxp,sc18is602b";
		reg = <0x2f>;

		spi-ade@2 {
			/* Using spidev compatible is warned loudly,
			   thus use another equivalent compatible id
			from spidev.*/

			compatible = "rohm,dh2228fv";
			reg = <2>;
		};
	};

};


&main_i2c0 {

	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;
	clock-frequency = <100000>;

	/*
	for now this expander controls the WP eeprom and allows PHY reset
	without resetting the entire system (SYS_RESET). Local_PG - self supervision
	*/

	//PCM schematic
	exp1: gpio1@77 {
		status = "okay";
		compatible = "ti,tca9539";
		reg = <0x77>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names = "PHY_RESET","P01","P02","P03",
				  "P04","P05","P06","P07","P10",
				  "P11","P12","P13","P14","P15",
				  "LOCAL_PG","EPPROM_WP";
		vcc-supply = <&vdd_3v3>;

		/* PHY_RESET pin configured by default in output high state to prevent keep PHYs constantly in reset
		   because kernel driver for tca9539 expander sets all pin in low state by default.
		*/
		phy_reset_hog {
			gpio-hog;
			gpios = <0 GPIO_ACTIVE_HIGH>;
			output-high; 
		};

	};

	//PMB schematic (status led/button expander)
	status_exp2: gpio2@74 {
		status = "disabled";
		compatible = "ti,tca9539";
		reg = <0x74>;
		gpio-controller;
		#gpio-cells = <2>;
		gpio-line-names = "LED0","LED1","LED2","LED3",
                                  "LED4","LED5","P06","P07","BUTTON0",
                                  "BUTTON1","BUTTON2","BUTTON3","BUTTON4","BUTTON5",
                                  "P16","P17";

		interrupt-controller;
		interrupt-parent = <&main_gpio0>; //to change
		#interrupt-cells = <2>;
		interrupts = <7 IRQ_TYPE_LEVEL_LOW>; //interrupt from one of the buttons comes on GPIO0_7

		vcc-supply = <&vdd_3v3>;

	};	

	/* 
	 Manufacturer of this eeprom is STMicroelectronic
         but the at24 driver does not contain ST memory in the "compatible" parameter 

	For now this eeprom is utilized by u-boot to board detection mechanism.
	This memory should not be written from linux level to avoid destroying data
	related to specific hwardware version.
	*/
	eeprom@56 {
		compatible = "st,24c04", "atmel,24c04";
		status = "disabled";
		reg = <0x56>;
		pagesize = <16>; 
		size = <512>;  /* total eeprom size in bytes*/
		no-read-rollover;
		address-width = <8>;
		wp-gpios = <&exp1 17 GPIO_ACTIVE_LOW>;
		vcc-supply = <&vdd_3v3>;
	};

	/* temperature sensor */

	lm75: tmp-sens@48 {
		status="okay";
		compatible = "national,lm75";
		reg = <0x48>;
		vs-supply = <&vdd_3v3>;
	};

	/* one of those two RTC will be used */

	ds1338: rtc1@68 {
		status = "okay";
		compatible = "dallas,ds1338";
		reg = <0x68>;		
	};

	pcf85363: rtc2@51 {
		status = "okay";
		compatible = "nxp,pcf85363";
		reg = <0x51>;
    };

	
	
};

&main_i2c2 {
    status = "disabled";
};

&main_i2c3 {
	status = "disabled";
};

&mcu_spi0 {
	status = "disabled";
};

&mcu_spi1 {
	status = "disabled";
};

/* mcu_gpio0 is reserved for mcu firmware usage */
&mcu_gpio0 {
	status = "reserved";
};


/* NAND/EMMC */
&sdhci0 {
         vmmc-supply = <&vdd_1v8>;
         vqmmc-supply = <&vdd_1v8>;
         bus-width = <8>;
         non-removable;
         ti,driver-strength-ohm = <50>;
         disable-wp;
};

/* SD/MMC */
&sdhci1 {
	vmmc-supply = <&vdd_3v3>;
	pinctrl-names = "default";
	bus-width = <4>;
	pinctrl-0 = <&main_mmc1_pins_default>;
	ti,driver-strength-ohm = <50>;
	disable-wp;
	cd-gpios = <&main_gpio1 77 GPIO_ACTIVE_LOW>;
};

&serdes_ln_ctrl {
	idle-states = <AM64_SERDES0_LANE0_USB>;
};

&serdes_wiz0 {
	status = "okay";
};

&serdes0 {
	serdes0_usb_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_USB3>;
		resets = <&serdes_wiz0 1>;
	};
};

&usbss0 {
	ti,vbus-divider;
};

&usb0 {
	dr_mode = "host";
	maximum-speed = "super-speed";
	pinctrl-names = "default";
	pinctrl-0 = <&main_usb0_pins_default>;
	phys = <&serdes0_usb_link>;
	phy-names = "cdns3,usb3-phy";
};

/************************************ NETWORK ****************************************/

&cpsw3g {
	pinctrl-names = "default";
	pinctrl-0 = <&cpsw_mdio0_pins_default
		     &rgmii1_io_bus_pins_default
		     &rgmii2_service_pins_default
	>;

	cpts@3d000 {
		ti,pps = <7 1>;
	};
};

&cpsw_port1 {
	status = "okay";
	phy-mode = "rgmii-rxid";
	phy-handle = <&cpsw3g_phy2>;
};

&cpsw_port2 {
	status = "okay";
	phy-mode = "rgmii-rxid";
	phy-handle = <&cpsw3g_phy1>;
};



&icssg0_mdio {

	pinctrl-names = "default";
	pinctrl-0 = <&pru_icssg0_mdio0_pins_default>;

	icssg0_phy3: ethernet-phy@3 {
                reg = <3>;
		adi,rx-internal-delay-ps = <2000>;
		adi,tx-internal-delay-ps = <2000>;
		adi,fifo-depth-bits = <8>;
        };

	icssg0_phy4: ethernet-phy@4 {  
                reg = <4>;
		adi,rx-internal-delay-ps = <2000>;
		adi,tx-internal-delay-ps = <2000>;
		adi,fifo-depth-bits = <8>;
        };
};



/*cpsw3g_mdio is children node of cpsw3g and pimux is specified for cpsw3g.
So it is not necessary to explicit define pinux here, like in icssg1_mdio node */

&cpsw3g_mdio {
	cpsw3g_phy1: ethernet-phy@1 {
		reg = <1>;
		adi,rx-internal-delay-ps = <2000>;
		adi,tx-internal-delay-ps = <2000>;
		adi,fifo-depth-bits = <8>;
		
	};

	cpsw3g_phy2: ethernet-phy@2 {
		reg = <2>;
		adi,rx-internal-delay-ps = <2000>;
		adi,tx-internal-delay-ps = <2000>;
		adi,fifo-depth-bits = <8>;
	};
};


&icssg1_iep0 {
	pinctrl-names = "default";
	pinctrl-0 = <&icssg1_iep0_pins_default>;
};

&icssg0_iep0 {
         pinctrl-names = "default";
         pinctrl-0 = <&icssg0_iep0_pins_default>;
};


#define TS_OFFSET(pa, val)     (0x4+(pa)*4) (0x10000 | val)



&timesync_router {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_cpts_pps>;

	/* Example of the timesync routing */
	mcu_cpts_pps: mcu-cpts-pps {
		pinctrl-single,pins = <
				/* pps [cpts genf1] in22 -> out37 [cpts hw8_push] */
				TS_OFFSET(37, 22)
				/* pps [cpts genf1] in22 -> out25 [SYNC1_OUT pin] */
				TS_OFFSET(25, 22)
				>;
	};
};

&mailbox0_cluster2 {
	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
		ti,mbox-rx = <0 0 2>;
		ti,mbox-tx = <1 0 2>;
	};

	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
		ti,mbox-rx = <2 0 2>;
		ti,mbox-tx = <3 0 2>;
	};
};

&mailbox0_cluster3 {
	status = "disabled";
};

&mailbox0_cluster4 {
	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
		ti,mbox-rx = <0 0 2>;
		ti,mbox-tx = <1 0 2>;
	};

	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
		ti,mbox-rx = <2 0 2>;
		ti,mbox-tx = <3 0 2>;
	};
};

&mailbox0_cluster5 {
	status = "disabled";
};

&mailbox0_cluster6 {
	mbox_m4_0: mbox-m4-0 {
		ti,mbox-rx = <0 0 2>;
		ti,mbox-tx = <1 0 2>;
	};
};

&mailbox0_cluster7 {
	status = "disabled";
};

&pcie0_rc {
	status = "disabled";
};

&pcie0_ep {
	status = "disabled";
};

&main_r5fss0_core0 {
	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
	memory-region = <&main_r5fss0_core0_dma_memory_region>,
			<&main_r5fss0_core0_memory_region>;
};

&main_r5fss0_core1 {
	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
	memory-region = <&main_r5fss0_core1_dma_memory_region>,
			<&main_r5fss0_core1_memory_region>;
};

&main_r5fss1_core0 {
	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
	memory-region = <&main_r5fss1_core0_dma_memory_region>,
			<&main_r5fss1_core0_memory_region>;
};

&main_r5fss1_core1 {
	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
	memory-region = <&main_r5fss1_core1_dma_memory_region>,
			<&main_r5fss1_core1_memory_region>;
};

&mcu_m4fss {
	mboxes = <&mailbox0_cluster6 &mbox_m4_0>;
	memory-region = <&mcu_m4fss_dma_memory_region>,
			<&mcu_m4fss_memory_region>;
};

&tscadc0 {
	status = "disabled";
};

#if 0
&ospi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&ospi0_pins_default>;

	flash@0{
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <8>;
		spi-rx-bus-width = <8>;
		spi-max-frequency = <25000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <4>;
		cdns,phy-mode;
		#address-cells = <1>;
		#size-cells = <1>;
	};
};
#endif

&main_mcan0 {
	status = "disabled";
};

&main_mcan1 {
	status = "disabled";
};




&ecap0 {
	/* PWM is available on Pin 1 of header J3 */
	pinctrl-names = "default";
	pinctrl-0 = <&main_ecap0_pins_default>;
};

&main_spi1 {
	#address-cells = <1>;
        #size-cells = <0>;
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&main_spi1_pins_default>;
        ti,spi-num-cs = <2>;
	ti,pindir-d0-out-d1-in;

	slb9670: slb9670@0 {
            compatible = "infineon,slb9670";
            reg = <0>;      /* CS0 */
            #address-cells = <1>;
            #size-cells = <0>;
            spi-max-frequency = <1000000>;
            status = "okay";
       };
};

&main_spi0 {

	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	pinctrl-names = "default";
	pinctrl-0 = <&main_spi0_pins_default>;
	ti,pindir-d0-out-d1-in;
	ti,spi-num-cs = <2>;
	
	/* allows control ADC from linux user space */
	spidev1: spidev@0 {
             compatible = "demospi"; /* spidev driver was patched to add this device name to OF array */
             reg = <0>;      /* CS0 */
             #address-cells = <1>;
             #size-cells = <0>;
             spi-max-frequency = <1000000>;
        };
};

I noticed that actually CPSW port is a problem... It is crashing with message NETDEV WATCHDOG: eth1 (am65-cpsw-nuss): transmit queue 0 timed out
[  482.149168] am65-cpsw-nuss 8000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:6776 dql_avail:-90 free_desc:515

Hi Jakub,

Could you please attach the portion of the watchdog timeout that the kernel prints out?

Thanks,

Schuyler

Hello Schuyler

Sorry for late response, I was out of office.

Sure, below is watchdog error that pop up after 2-3 sec when I connected ethernet cable to eth1 port.

root@puma:~# [ 44.135231] ------------[ cut here ]------------
[ 44.135249] NETDEV WATCHDOG: eth1 (am65-cpsw-nuss): transmit queue 0 timed out
[ 44.135328] WARNING: CPU: 0 PID: 11 at net/sched/sch_generic.c:467 dev_watchdog+0x368/0x370
[ 44.135358] Modules linked in: cdns3 udc_core roles usbcore usb_common crct10dif_ce cdns3_ti rti_wdt ti_k3_r5_remoteproc virtio_rpmsg_bus ti_k3_m4_remoteproc sa2ul sha512_generic authenc at24 rtc_pcf85363 rtc_ds1307 cfg80211 rfkill sch_fq_codel fuse ipv6
[ 44.135431] CPU: 0 PID: 11 Comm: ksoftirqd/0 Not tainted 5.10.168-rt83+ #1
[ 44.135439] Hardware name: ABB Puma device (DT)
[ 44.135444] pstate: 60000005 (nZCv daif -PAN -UAO -TCO BTYPE=--)
[ 44.135452] pc : dev_watchdog+0x368/0x370
[ 44.135461] lr : dev_watchdog+0x368/0x370
[ 44.135470] sp : ffff80001147bc10
[ 44.135473] x29: ffff80001147bc10 x28: ffff00000187eb00
[ 44.135482] x27: 0000000000000004 x26: ffff00000187d4b0
[ 44.135490] x25: 0000000000000180 x24: 00000000ffffffff
[ 44.135498] x23: 0000000000000000 x22: ffff00000187d3e0
[ 44.135505] x21: ffff800011219000 x20: ffff00000187d000
[ 44.135514] x19: 0000000000000000 x18: ffffffffffffffff
[ 44.135521] x17: 00004a22ffffb5dd x16: 0000000000000000
[ 44.135530] x15: ffff80001137cba6 x14: ffffffffffffffff
[ 44.135538] x13: ffff80001137cb99 x12: fffffffffffc8ecf
[ 44.135546] x11: ffff800011232118 x10: ffff80001123d498
[ 44.135554] x9 : ffff80001147bc10 x8 : 64656d6974203020
[ 44.135561] x7 : 6575657571207469 x6 : 000000000000000c
[ 44.135569] x5 : ffff00007fbd1b30 x4 : 0000000000000000
[ 44.135576] x3 : 0000000000000027 x2 : 0000000000000000
[ 44.135584] x1 : 0000000000000000 x0 : ffff0000000d9e00
[ 44.135593] Call trace:
[ 44.135597] dev_watchdog+0x368/0x370
[ 44.135606] call_timer_fn.constprop.0+0x24/0x80
[ 44.135619] __run_timers.part.0+0x254/0x2cc
[ 44.135628] run_timer_softirq+0x3c/0x74
[ 44.135636] efi_header_end+0x10c/0x238
[ 44.135645] run_ksoftirqd+0x54/0xc0
[ 44.135653] smpboot_thread_fn+0x2e4/0x330
[ 44.135661] kthread+0x18c/0x1a0
[ 44.135670] ret_from_fork+0x10/0x38
[ 44.135680] ---[ end trace 0000000000000002 ]---
[ 45.135998] am65-cpsw-nuss 8000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:6716 dql_avail:-90 free_desc:515
[ 50.023235] am65-cpsw-nuss 8000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:11604 dql_avail:-90 free_desc:515
[ 55.143236] am65-cpsw-nuss 8000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:16724 dql_avail:-90 free_desc:515
[ 60.007236] am65-cpsw-nuss 8000000.ethernet eth1: txq:0 DRV_XOFF:0 tmo:21588 dql_avail:-90 free_desc:515

Hi Jakub.

Just to align lets to work on one interface eth1 since this is the one showing the error. Usually the watchdog timeout usually happens when there is an issue with clocking. This sometimes is a pin mux issue related to the TX clock line. Please do not attach any other cables to the other ports.

Does ethtool eth1 show a link connected?

Does ethtool -S eth1  show any packets being transmitted?

Best Regards,

Schuyler

Hi Schuyler

Since on our board we are using ADIN1200 not DP83822 or DP83867 for which TMDS64GPEVM  device tree was prepared should I modify something in .dtsi files?

eht1 -S eth1 just after watchdog error shows:

p0_rx_good_frames: 1
p0_rx_broadcast_frames: 0
p0_rx_multicast_frames: 1
p0_rx_crc_errors: 0
p0_rx_oversized_frames: 0
p0_rx_undersized_frames: 0
p0_ale_drop: 0
p0_ale_overrun_drop: 0
p0_rx_octets: 94
p0_tx_good_frames: 40
p0_tx_broadcast_frames: 24
p0_tx_multicast_frames: 16
p0_tx_octets: 3762
p0_tx_64B_frames: 6
p0_tx_65_to_127B_frames: 35
p0_tx_128_to_255B_frames: 0
p0_tx_256_to_511B_frames: 0
p0_tx_512_to_1023B_frames: 0
p0_tx_1024B_frames: 0
p0_net_octets: 3856
p0_rx_bottom_fifo_drop: 0
p0_rx_port_mask_drop: 0
p0_rx_top_fifo_drop: 0
p0_ale_rate_limit_drop: 0
p0_ale_vid_ingress_drop: 0
p0_ale_da_eq_sa_drop: 0
p0_ale_block_drop: 0
p0_ale_secure_drop: 0
p0_ale_auth_drop: 0
p0_ale_unknown_ucast: 0
p0_ale_unknown_ucast_bytes: 0
p0_ale_unknown_mcast: 0
p0_ale_unknown_mcast_bytes: 0
p0_ale_unknown_bcast: 0
p0_ale_unknown_bcast_bytes: 0
p0_ale_pol_match: 0
p0_ale_pol_match_red: 0
p0_ale_pol_match_yellow: 0
p0_ale_mcast_sa_drop: 0
p0_ale_dual_vlan_drop: 0
p0_ale_len_err_drop: 0
p0_ale_ip_next_hdr_drop: 0
p0_ale_ipv4_frag_drop: 0
p0_tx_mem_protect_err: 0
p0_tx_pri0: 40
p0_tx_pri1: 0
p0_tx_pri2: 0
p0_tx_pri3: 0
p0_tx_pri4: 0
p0_tx_pri5: 0
p0_tx_pri6: 0
p0_tx_pri7: 0
p0_tx_pri0_bcnt: 3762
p0_tx_pri1_bcnt: 0
p0_tx_pri2_bcnt: 0
p0_tx_pri3_bcnt: 0
p0_tx_pri4_bcnt: 0
p0_tx_pri5_bcnt: 0
p0_tx_pri6_bcnt: 0
p0_tx_pri7_bcnt: 0
p0_tx_pri0_drop: 0
p0_tx_pri1_drop: 0
p0_tx_pri2_drop: 0
p0_tx_pri3_drop: 0
p0_tx_pri4_drop: 0
p0_tx_pri5_drop: 0
p0_tx_pri6_drop: 0
p0_tx_pri7_drop: 0
p0_tx_pri0_drop_bcnt: 0
p0_tx_pri1_drop_bcnt: 0
p0_tx_pri2_drop_bcnt: 0
p0_tx_pri3_drop_bcnt: 0
p0_tx_pri4_drop_bcnt: 0
p0_tx_pri5_drop_bcnt: 0
p0_tx_pri6_drop_bcnt: 0
p0_tx_pri7_drop_bcnt: 0
rx_good_frames: 209
rx_broadcast_frames: 24
rx_multicast_frames: 185
rx_pause_frames: 0
rx_crc_errors: 0
rx_align_code_errors: 0
rx_oversized_frames: 0
rx_jabber_frames: 0
rx_undersized_frames: 0
rx_fragments: 0
ale_drop: 169
ale_overrun_drop: 0
rx_octets: 20522
tx_good_frames: 1
tx_broadcast_frames: 0
tx_multicast_frames: 1
tx_pause_frames: 0
tx_deferred_frames: 0
tx_collision_frames: 0
tx_single_coll_frames: 0
tx_mult_coll_frames: 0
tx_excessive_collisions: 0
tx_late_collisions: 0
rx_ipg_error: 0
tx_carrier_sense_errors: 0
tx_octets: 94
tx_64B_frames: 12
tx_65_to_127B_frames: 175
tx_128_to_255B_frames: 23
tx_256_to_511B_frames: 0
tx_512_to_1023B_frames: 0
tx_1024B_frames: 0
net_octets: 20616
rx_bottom_fifo_drop: 0
rx_port_mask_drop: 169
rx_top_fifo_drop: 0
ale_rate_limit_drop: 0
ale_vid_ingress_drop: 0
ale_da_eq_sa_drop: 0
ale_block_drop: 0
ale_secure_drop: 0
ale_auth_drop: 0
ale_unknown_ucast: 0
ale_unknown_ucast_bytes: 0
ale_unknown_mcast: 185
ale_unknown_mcast_bytes: 18098
ale_unknown_bcast: 24
ale_unknown_bcast_bytes: 2424
ale_pol_match: 0
ale_pol_match_red: 0
ale_pol_match_yellow: 0
ale_mcast_sa_drop: 0
ale_dual_vlan_drop: 0
ale_len_err_drop: 0
ale_ip_next_hdr_drop: 0
ale_ipv4_frag_drop: 0
iet_rx_assembly_err: 0
iet_rx_assembly_ok: 0
iet_rx_smd_err: 0
iet_rx_frag: 0
iet_tx_hold: 0
iet_tx_frag: 0
tx_mem_protect_err: 0
tx_pri0: 1
tx_pri1: 0
tx_pri2: 0
tx_pri3: 0
tx_pri4: 0
tx_pri5: 0
tx_pri6: 0
tx_pri7: 0
tx_pri0_bcnt: 94
tx_pri1_bcnt: 0
tx_pri2_bcnt: 0
tx_pri3_bcnt: 0
tx_pri4_bcnt: 0
tx_pri5_bcnt: 0
tx_pri6_bcnt: 0
tx_pri7_bcnt: 0
tx_pri0_drop: 0
tx_pri1_drop: 0
tx_pri2_drop: 0
tx_pri3_drop: 0
tx_pri4_drop: 0
tx_pri5_drop: 0
tx_pri6_drop: 0
tx_pri7_drop: 0
tx_pri0_drop_bcnt: 0
tx_pri1_drop_bcnt: 0
tx_pri2_drop_bcnt: 0
tx_pri3_drop_bcnt: 0
tx_pri4_drop_bcnt: 0
tx_pri5_drop_bcnt: 0
tx_pri6_drop_bcnt: 0
tx_pri7_drop_bcnt: 0

BR

Jakub

Hi Jakub,

I apologize for the delay I will try to respond tomorrow to your thread.

Best Regards,

Schuyler

Hi Jakub,

Are you still having the issue?

After reviewing the pin mux it looks like your board is using IO set 2 for RGMII1. The TI EVM uses IO set 1 but that should not make a difference. I do not see an error with the pin mux.

Best Regards,

Schuyler