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PROCESSOR-SDK-AM335X: How to modify the CPU frequency on RT SDK?

Part Number: PROCESSOR-SDK-AM335X

Hi Team,

Could you tell me how to modify the CPU frequency on RT SDK?

The SDK version I use is "Linux-RT Processor SDK for AM335x 08.02.00.24".

I would like to know the current frequency and how to modify it.

Here is the information on my board and there is no file named "scaling_cur_freq" .

root@am335x-evm:/sys/devices/system/cpu/cpu0# ls
crash_notes       of_node           subsystem         uevent
crash_notes_size  power             topology

Could you tell me how to do it? Maybe tell me how to set dead-code frequency in driver?

  • Hey Woody,

    This question was already answered in this thread: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1186274/am3352-modify-cpu-frequency-on-rt-sdk

    Due to latency requirements, cpufreq is disabled in RT kernel.

    One way to modify the cpu frequency is to delete the unwanted frequencies from the cpu0_opp_table in kernel device tree am33xx.dtsi.

    Please let us know if you have any other questions regarding this.

    Regards,

    Randolph

  • Hi Sapp,

    Can I set fixed frequency into driver code? Could you tell me what's the file name and give a an example?

    Thanks.

  • Sure,

    The following patch should lock cpu0 at 800MHz:

    diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
    index d29cb4ec3fd2..e16c5287e6a5 100644
    --- a/arch/arm/boot/dts/am33xx.dtsi
    +++ b/arch/arm/boot/dts/am33xx.dtsi
    @@ -78,73 +78,11 @@ cpu0_opp_table: opp-table {
     		compatible = "operating-points-v2-ti-cpu";
     		syscon = <&scm_conf>;
     
    -		/*
    -		 * The three following nodes are marked with opp-suspend
    -		 * because the can not be enabled simultaneously on a
    -		 * single SoC.
    -		 */
    -		opp50-300000000 {
    -			opp-hz = /bits/ 64 <300000000>;
    -			opp-microvolt = <950000 931000 969000>;
    -			opp-supported-hw = <0x06 0x0010>;
    -			opp-suspend;
    -		};
    -
    -		opp100-275000000 {
    -			opp-hz = /bits/ 64 <275000000>;
    -			opp-microvolt = <1100000 1078000 1122000>;
    -			opp-supported-hw = <0x01 0x00FF>;
    -			opp-suspend;
    -		};
    -
    -		opp100-300000000 {
    -			opp-hz = /bits/ 64 <300000000>;
    -			opp-microvolt = <1100000 1078000 1122000>;
    -			opp-supported-hw = <0x06 0x0020>;
    -			opp-suspend;
    -		};
    -
    -		opp100-500000000 {
    -			opp-hz = /bits/ 64 <500000000>;
    -			opp-microvolt = <1100000 1078000 1122000>;
    -			opp-supported-hw = <0x01 0xFFFF>;
    -		};
    -
    -		opp100-600000000 {
    -			opp-hz = /bits/ 64 <600000000>;
    -			opp-microvolt = <1100000 1078000 1122000>;
    -			opp-supported-hw = <0x06 0x0040>;
    -		};
    -
    -		opp120-600000000 {
    -			opp-hz = /bits/ 64 <600000000>;
    -			opp-microvolt = <1200000 1176000 1224000>;
    -			opp-supported-hw = <0x01 0xFFFF>;
    -		};
    -
    -		opp120-720000000 {
    -			opp-hz = /bits/ 64 <720000000>;
    -			opp-microvolt = <1200000 1176000 1224000>;
    -			opp-supported-hw = <0x06 0x0080>;
    -		};
    -
    -		oppturbo-720000000 {
    -			opp-hz = /bits/ 64 <720000000>;
    -			opp-microvolt = <1260000 1234800 1285200>;
    -			opp-supported-hw = <0x01 0xFFFF>;
    -		};
    -
     		oppturbo-800000000 {
     			opp-hz = /bits/ 64 <800000000>;
     			opp-microvolt = <1260000 1234800 1285200>;
     			opp-supported-hw = <0x06 0x0100>;
     		};
    -
    -		oppnitro-1000000000 {
    -			opp-hz = /bits/ 64 <1000000000>;
    -			opp-microvolt = <1325000 1298500 1351500>;
    -			opp-supported-hw = <0x04 0x0200>;
    -		};
     	};
     
     	pmu@4b000000 {
    

    Regards,

    Randolph

  • Hi Randolph,

    Thanks for your information. Please take a look of my patch on am33xx.dtsi.

    As you see, I commented out unnecessary voltage but only 600M HZ.

    So I expect the voltage of Vdd(mpu) should be about 1.17 to 1.22V. But the result is 1.35V.

    It seems like the voltage is still in Turbo Mode or Nitro Mode according to the value of voltage.

    Do you have any ideas? 

    Also I have modified the am33xx.dtsi of u-boot-stage, the vdd of mpu still is 1.35V.

    If the frequency is 600M HZ, why Vdd(mpu) is 1.35V?

    diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
    index d29cb4ec3fd2..b71dde8c6d90 100644
    --- a/arch/arm/boot/dts/am33xx.dtsi
    +++ b/arch/arm/boot/dts/am33xx.dtsi
    @@ -83,6 +83,7 @@
     		 * because the can not be enabled simultaneously on a
     		 * single SoC.
     		 */
    +/*         
     		opp50-300000000 {
     			opp-hz = /bits/ 64 <300000000>;
     			opp-microvolt = <950000 931000 969000>;
    @@ -109,7 +110,7 @@
     			opp-microvolt = <1100000 1078000 1122000>;
     			opp-supported-hw = <0x01 0xFFFF>;
     		};
    -
    +*/
     		opp100-600000000 {
     			opp-hz = /bits/ 64 <600000000>;
     			opp-microvolt = <1100000 1078000 1122000>;
    @@ -121,7 +122,7 @@
     			opp-microvolt = <1200000 1176000 1224000>;
     			opp-supported-hw = <0x01 0xFFFF>;
     		};
    -
    +/*
     		opp120-720000000 {
     			opp-hz = /bits/ 64 <720000000>;
     			opp-microvolt = <1200000 1176000 1224000>;
    @@ -145,6 +146,7 @@
     			opp-microvolt = <1325000 1298500 1351500>;
     			opp-supported-hw = <0x04 0x0200>;
     		};
    +*/        
     	};
     
     	pmu@4b000000 {

     

  • Hi Woody,

    Since RT doesn't enable cpufreq framework, I don't think the VDD will be automatically adjusted based on the CPU clk. I will have to review the kernel code to understand how to set the VDD voltage. I am currently working on a critical task, likely would need more time to get back to you. Please ping on this thread if I didn't respond by end of next week.

  • Hi Bin,

    Thanks for you sharing and please take a look on this question when you are available.

    What I have done is to modify am33xx.dtsi and am335x-evmsk.dts on both u-boot and kernel stage.

    But the vdd_mpu still is 1.35V, I am concerned that the frequency is not modified successfully.

    Thanks.

     arch/arm/boot/dts/am335x-evmsk.dts |  2 +-
     arch/arm/boot/dts/am33xx.dtsi      | 56 ------------------------------
     2 files changed, 1 insertion(+), 57 deletions(-)
    
    diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
    index f5c893a13e0b..af2371cc9107 100644
    --- a/arch/arm/boot/dts/am335x-evmsk.dts
    +++ b/arch/arm/boot/dts/am335x-evmsk.dts
    @@ -352,7 +352,7 @@
     			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
     			regulator-name = "vdd_mpu";
     			regulator-min-microvolt = <912500>;
    -			regulator-max-microvolt = <1351500>;
    +			regulator-max-microvolt = <1122000>;
     			regulator-boot-on;
     			regulator-always-on;
     		};
    diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
    index d29cb4ec3fd2..e80517e9a75f 100644
    --- a/arch/arm/boot/dts/am33xx.dtsi
    +++ b/arch/arm/boot/dts/am33xx.dtsi
    @@ -83,68 +83,12 @@
     		 * because the can not be enabled simultaneously on a
     		 * single SoC.
     		 */
    -		opp50-300000000 {
    -			opp-hz = /bits/ 64 <300000000>;
    -			opp-microvolt = <950000 931000 969000>;
    -			opp-supported-hw = <0x06 0x0010>;
    -			opp-suspend;
    -		};
    -
    -		opp100-275000000 {
    -			opp-hz = /bits/ 64 <275000000>;
    -			opp-microvolt = <1100000 1078000 1122000>;
    -			opp-supported-hw = <0x01 0x00FF>;
    -			opp-suspend;
    -		};
    -
    -		opp100-300000000 {
    -			opp-hz = /bits/ 64 <300000000>;
    -			opp-microvolt = <1100000 1078000 1122000>;
    -			opp-supported-hw = <0x06 0x0020>;
    -			opp-suspend;
    -		};
    -
    -		opp100-500000000 {
    -			opp-hz = /bits/ 64 <500000000>;
    -			opp-microvolt = <1100000 1078000 1122000>;
    -			opp-supported-hw = <0x01 0xFFFF>;
    -		};
     
     		opp100-600000000 {
     			opp-hz = /bits/ 64 <600000000>;
     			opp-microvolt = <1100000 1078000 1122000>;
     			opp-supported-hw = <0x06 0x0040>;
     		};
    -
    -		opp120-600000000 {
    -			opp-hz = /bits/ 64 <600000000>;
    -			opp-microvolt = <1200000 1176000 1224000>;
    -			opp-supported-hw = <0x01 0xFFFF>;
    -		};
    -
    -		opp120-720000000 {
    -			opp-hz = /bits/ 64 <720000000>;
    -			opp-microvolt = <1200000 1176000 1224000>;
    -			opp-supported-hw = <0x06 0x0080>;
    -		};
    -
    -		oppturbo-720000000 {
    -			opp-hz = /bits/ 64 <720000000>;
    -			opp-microvolt = <1260000 1234800 1285200>;
    -			opp-supported-hw = <0x01 0xFFFF>;
    -		};
    -
    -		oppturbo-800000000 {
    -			opp-hz = /bits/ 64 <800000000>;
    -			opp-microvolt = <1260000 1234800 1285200>;
    -			opp-supported-hw = <0x06 0x0100>;
    -		};
    -
    -		oppnitro-1000000000 {
    -			opp-hz = /bits/ 64 <1000000000>;
    -			opp-microvolt = <1325000 1298500 1351500>;
    -			opp-supported-hw = <0x04 0x0200>;
    -		};
     	};
     
     	pmu@4b000000 {
    -- 
    2.17.1

  • Hi Bin, 

    I think the removal of opp table may not work, because I modify the opp table and reserve the opp50 only.

    	cpu0_opp_table: opp-table {
    		compatible = "operating-points-v2-ti-cpu";
    		syscon = <&scm_conf>;
    
    		/*
    		 * The three following nodes are marked with opp-suspend
    		 * because the can not be enabled simultaneously on a
    		 * single SoC.
    		 */
    
    		opp50-300000000 {
    			opp-hz = /bits/ 64 <300000000>;
    			opp-microvolt = <950000 931000 969000>;
    			opp-supported-hw = <0x06 0x0010>;
    			opp-suspend;
    		};
    	};

    make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- am335x-evmsk.dtb

    then replace the dtb with mine.

    According to the datasheet, CPSW should not be supported. But the CPSW is still enabled.

    Does it mean the way you provided is not effective ?

  • Hi Woody,

    The Datasheet only means the listed modules are not supported or have reduced performance, but the modules won't be automatically disabled in OOP50. You would have to manually disable those modules in OPP50.

  • Hi Bin,

    Thanks for your kindly answer.

    I still need to check the value of MPU frequency on RT SDK.

    I am not convinced that the frequency is 300M HZ but the vdd_mpu is 1.35V.

    Please help on it while you are available. Thank you.

  • Hi Bin,

    Here is more information share with you.

    I try to enable Kconfig in the kernel menuconfig.

    #
    # CPU Frequency scaling
    #
    CONFIG_CPU_FREQ=y
    CONFIG_CPU_FREQ_GOV_ATTR_SET=y
    CONFIG_CPU_FREQ_GOV_COMMON=y
    CONFIG_CPU_FREQ_STAT=y
    # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
    # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
    CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
    # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
    # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
    CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
    CONFIG_CPU_FREQ_GOV_POWERSAVE=y
    CONFIG_CPU_FREQ_GOV_USERSPACE=y
    CONFIG_CPU_FREQ_GOV_ONDEMAND=y
    CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y

    After building it, there is still no cpufreq folder under /sys/device/system/cpu.

    I really don't know how to resolve it.

  • Hi Bin:

    This is the AM335 RT LINUX for CPU_Freq issue, customer Delta posted the below.

    And I have read it, tested it.

     https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1264579/processor-sdk-am335x-how-to-modify-the-cpu-frequency-on-rt-sdk/4794609#4794609

     

    The issue is clear:

                   Native Linux has the CPU Freq Scaling fine tune.

                   But the 8.2 RT Linux has no this function for allowing user to do that.

     

    You can see the native Linux has this:

                   root@am335x-evm:~# echo 800000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_settspeed

    root@am335x-evm:~# cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq

     

    I think, the fastest ways are:

    1. Have the LCPD team to fix the user space file system.
    2. Or, maybe Customer can copy the Native Filesystem from Native Linux to RT Linux?

    Any comment?

    BR Rio

  • Hi Bin.

    In short, 

       The posted picture is to say the "CPU freq" tool is missing in the RT-Linux 8.2.

       This is the missing part. Customer needs this tool on the RT 8.2 SDK.

    Thanks.

    BR Rio

  • Rio,

    To prevent DVFS affecting RT kernel latency, CPUFreq is disabled in RT kernel.

    If CPUFreq is needed, non_RT kernel should be used instead.

  • Hi Bin:

    Customer needs the RT, but he doesn't care the kernel latency drifting.

    May you show him the way how to config the CPU working at 600Mhz in a simple/direct way?

    Thanks.

    BR Rio

  • Rio,

    Customer needs the RT, but he doesn't care the kernel latency drifting.

    I don't see the point. What is the benefit of using RT kernel then?

    May you show him the way how to config the CPU working at 600Mhz in a simple/direct way?

    As Randolph commented above, you can remove all all other OPPs from kernel DTS and only keep OPP100-600MHz or OPP120-600MHz.

  • Hi Bin,

    Here is my device with "opp100-300000000" and the clk_summary is as below.

    You can see the dpll_mpu_ck is 1G but I'm not sure it means frequency or not.

    Could you take a look on it? The value of dpll_mpu_ck should be 300M ?

    Thanks.

    root@am335x-evm:~# cat /sys/kernel/debug/clk/clk_summary
    
                                     enable  prepare  protect                                duty
       clock                          count    count    count        rate   accuracy phase  cycle
    ---------------------------------------------------------------------------------------------
     tclkin_ck                            0        0        0    12000000          0     0  50000
     virt_26000000_ck                     0        0        0    26000000          0     0  50000
     virt_25000000_ck                     1        1        0    25000000          0     0  50000
        sys_clkin_ck                      7       22        0    25000000          0     0  50000
           timer6_fck                     0        1        0    25000000          0     0  50000
              l4ls-clkctrl:00b8:0         0        1        0    25000000          0     0  50000
           timer3_fck                     0        1        0    25000000          0     0  50000
              l4ls-clkctrl:004c:0         0        1        0    25000000          0     0  50000
           timer7_fck                     0        1        0    25000000          0     0  50000
              l4ls-clkctrl:0044:0         0        1        0    25000000          0     0  50000
           timer5_fck                     0        1        0    25000000          0     0  50000
              l4ls-clkctrl:00b4:0         0        1        0    25000000          0     0  50000
           timer4_fck                     0        1        0    25000000          0     0  50000
              l4ls-clkctrl:0050:0         0        1        0    25000000          0     0  50000
           timer2_fck                     1        1        0    25000000          0     0  50000
              l4ls-clkctrl:0048:0         2        2        0    25000000          0     0  50000
           timer1_fck                     1        1        0    25000000          0     0  50000
              l4-wkup-clkctrl:00c4:0       2        2        0    25000000          0     0  50000
           dpll_per_ck                    1        2        0   960000000          0     0  50000
              usbotg_fck                  0        1        0   960000000          0     0  50000
                 l3s-clkctrl:0000:0       0        1        0   960000000          0     0  50000
              dpll_per_m2_ck              2        4        0   192000000          0     0  50000
                 mmc_clk                  2        3        0    96000000          0     0  50000
                    l4ls-clkctrl:0004:0       1        1        0    96000000          0     0  50000
                    l4ls-clkctrl:00bc:0       1        1        0    96000000          0     0  50000
                    l3s-clkctrl:00dc:0       0        1        0    96000000          0     0  50000
                 clk_24mhz                0        1        0    24000000          0     0  50000
                    clkdiv32k_ck          0        1        0       32786          0     0  50000
                       clk-24mhz-clkctrl:0000:0       0        4        0       32786          0     0  50000
                          wdt1_fck        0        1        0       32786          0     0  50000
                             l4-wkup-clkctrl:00d4:0       0        1        0       32786          0     0  50000
                          l4ls-clkctrl:0074:18       0        2        0       32786          0     0  50000
                          l4ls-clkctrl:0078:18       0        2        0       32786          0     0  50000
                          l4ls-clkctrl:007c:18       0        2        0       32786          0     0  50000
                 dpll_per_m2_div4_ck       0        9        0    48000000          0     0  50000
                    l4ls-clkctrl:0000:0       0        1        0    48000000          0     0  50000
                    l4ls-clkctrl:000c:0       0        1        0    48000000          0     0  50000
                    l4ls-clkctrl:0010:0       0        1        0    48000000          0     0  50000
                    l4ls-clkctrl:0014:0       0        1        0    48000000          0     0  50000
                    l4ls-clkctrl:0018:0       0        1        0    48000000
        0     0  50000
                    l4ls-clkctrl:0034:0       0        1        0    48000000          0     0  50000
                    l4ls-clkctrl:0038:0       0        1        0    48000000          0     0  50000
                    l4ls-clkctrl:003c:0       0        1        0    48000000          0     0  50000
                    l4ls-clkctrl:0040:0       0        1        0    48000000          0     0  50000
                 dpll_per_m2_div4_wkupdm_ck       1        2        0    48000000          0     0  50000
                    l4-wkup-clkctrl:00b4:0       1        1        0    48000000          0     0  50000
                    l4-wkup-clkctrl:00b8:0       0        1        0    48000000          0     0  50000
           dpll_disp_ck                   0        1        0    25000000          0     0  50000
              dpll_disp_m2_ck             0        1        0    25000000          0     0  50000
                 lcd_gclk                 0        1        0    25000000          0     0  50000
                    lcdc-clkctrl:0000:0       0        1        0    25000000          0     0  50000
           dpll_ddr_ck                    1        1        0   277083333          0     0  50000
              dpll_ddr_m2_ck              2        2        0   277083333          0     0  50000
                 dpll_ddr_m2_div2_ck       1        1        0   138541666          0     0  50000
                    l3-clkctrl:0004:0       1        1        0   138541666          0     0  50000
           dpll_mpu_ck                    1        1        0  1000000000          0     0  50000
              dpll_mpu_m2_ck              4        4        0  1000000000          0     0  50000
                 mpu-clkctrl:0004:0       1        1        0  1000000000          0     0  50000
           dpll_core_ck                   1        1        0  1000000000          0     0  50000
              dpll_core_x2_ck             2        2        0  2000000000          0     0  50000
                 dpll_core_m6_ck          0        0        0   500000000          0     0  50000
                 dpll_core_m5_ck          2        2        0   250000000          0     0  50000
                    cpsw_cpts_rft_clk       1        1        0   250000000          0     0  50000
                    cpsw_125mhz_gclk       1        1        0   125000000          0     0  50000
                       cpsw-125mhz-clkctrl:0014:0       1        1        0   125000000          0     0  50000
                 dpll_core_m4_ck          5        6        0   200000000          0     0  50000
                    gfx_fclk_clksel_ck       0        0        0   200000000          0     0  50000
                       gfx_fck_div_ck       0        0        0   200000000          0     0  50000
                          gfx-l3-clkctrl:0004:0       0        0        0   200000000          0     0  50000
                    sysclk_div_ck         0        0        0   200000000          0     0  50000
                    l4hs_gclk             2        2        0   200000000          0     0  50000
                       l4hs-clkctrl:0000:0       1        1        0   200000000          0     0  50000
                    l4_rtc_gclk           0        0        0   100000000          0     0  50000
                    dpll_core_m4_div2_ck      11       12        0   100000000          0     0  50000
                       l4ls_gclk          5       11        0   100000000          0     0  50000
                          ehrpwm2_tbclk       0        0        0   100000000          0     0  50000
                          ehrpwm1_tbclk       0        0        0   100000000          0     0  50000
                          ehrpwm0_tbclk       0        0        0   100000000          0     0  50000
                          l4ls-clkctrl:0008:0       0        1        0   100000000          0     0  50000
                          l4ls-clkctrl:0028:0       1        1        0   100000000          0     0  50000
                          l4ls-clkctrl:0074:0       1        1        0   100000000          0     0  50000
                          l4ls-clkctrl:0078:0       1        1        0   100000000          0     0  50000
                          l4ls-clkctrl:007c:0       1        1        0   100000000          0     0  50000
                          l4ls-clkctrl:0094:0       0        1        0   100000000          0     0  50000
                          l4ls-clkctrl:009c:0       0        1        0   100000000          0     0  50000
                          l4ls-clkctrl:00a0:0       0        1        0   100000000          0     0  50000
                          l4ls-clkctrl:00d4:0       0        1        0   100000000          0     0  50000
                          l4ls-clkctrl:00d8:0       0        1        0   100000000          0     0  50000
                          l4ls-clkctrl:00f8:0       0        0        0   100000000          0     0  50000
                       l4fw_gclk          1        1        0   100000000          0     0  50000
                       l3s_gclk           8        8        0   100000000          0     0  50000
                          l3s-clkctrl:0014:0       1        1        0   100000000          0     0  50000
                       ieee5000_fck       0        0        0   100000000          0     0  50000
                       l4-wkup-clkctrl:0004:0       1        1        0   100000000          0     0  50000
                       l4-wkup-clkctrl:0008:0       1        1        0   100000000          0     0  50000
                       l4-wkup-clkctrl:000c:0       1        1        0   100000000          0     0  50000
                       l4-wkup-aon-clkctrl:0000:0       0        1        0   100000000          0     0  50000
                    mmu_fck               0        0        0   200000000          0     0  50000
                    l3_gclk               8        9        0   200000000          0     0  50000
                       pruss_ocp_gclk       0        0        0   200000000          0     0  50000
                          pruss-ocp-clkctrl:0000:0       0        0        0   200000000          0     0  50000
                       l3-clkctrl:0000:0       1        1        0   200000000          0     0  50000
                       l3-clkctrl:0008:0       1        1        0   200000000          0     0  50000
                       l3-clkctrl:007c:0       0        1        0   200000000          0     0  50000
                       l3-clkctrl:0098:0       1        1        0   200000000          0     0  50000
                       l3-clkctrl:00b8:0       1        1        0   200000000          0     0  50000
                       l3-clkctrl:00bc:0       1        1        0   200000000          0     0  50000
                       l3-clkctrl:00d8:0       1        1        0   200000000          0     0  50000
                       l3-clkctrl:00dc:0       1        1        0   200000000          0     0  50000
                    l3-aon-clkctrl:0000:30       0        2        0   200000000          0     0  50000
                       l3-aon-clkctrl:0000:20       0        1        0   200000000          0     0  50000
                          l3-aon-clkctrl:0000:24       0        1        0    50000000          0     0  50000
                             l3-aon-clkctrl:0000:0       0        1        0    50000000          0     0  50000
                       l3-aon-clkctrl:0000:22       0        0        0   200000000          0     0  50000
                          l3-aon-clkctrl:0000:27       0        0        0    50000000          0     0  50000
           rng_fck                        1        1        0    25000000          0     0  50000
              l4ls-clkctrl:0058:0         1        1        0    25000000          0     0  50000
           aes0_fck                       0        1        0    25000000          0     0  50000
              l3-clkctrl:0070:0           0        1        0    25000000          0     0  50000
           sha0_fck                       0        0        0    25000000          0     0  50000
           smartreflex1_fck               0        1        0    25000000          0     0  50000
              l4-wkup-clkctrl:00c8:0       0        1        0    25000000          0     0  50000
           smartreflex0_fck               0        1        0    25000000          0     0  50000
              l4-wkup-clkctrl:00c0:0       0        1        0    25000000          0     0  50000
           mcasp1_fck                     0        1        0    25000000          0     0  50000
              l3s-clkctrl:004c:0          0        1        0    25000000          0     0  50000
           mcasp0_fck                     0        1        0    25000000          0     0  50000
              l3s-clkctrl:0018:0          0        1        0    25000000          0     0  50000
           dcan1_fck                      0        2        0    25000000          0     0  50000
              l4ls-clkctrl:008c:0         0        1        0    25000000          0     0  50000
           dcan0_fck                      0        2        0    25000000          0     0  50000
              l4ls-clkctrl:0088:0         0        1        0    25000000          0     0  50000
           adc_tsc_fck                    0        1        0    25000000          0     0  50000
              l4-wkup-clkctrl:00bc:0       0        1        0    25000000          0     0  50000
           l3-aon-clkctrl:0000:19         0        1        0    25000000          0     0  50000
           l4-cefuse-clkctrl:0020:0       0        0        0    25000000          0     0  50000
     virt_24000000_ck                     0        0        0    24000000          0     0  50000
     virt_19200000_ck                     0        0        0    19200000          0     0  50000
     clk_rc32k_ck                         0        1        0       32000          0     0  50000
        gpio0_dbclk_mux_ck                0        1        0       32000          0     0  50000
           l4-wkup-clkctrl:0008:18        0        2        0       32000          0     0  50000
     clk_32768_ck                         1        1        0       32768          0     0  50000
        sysclkout_pre_ck                  1        1        0       32768          0     0  50000
           clkout2_div_ck                 1        1        0       32768          0     0  50000
              clkout2_ck                  1        1        0       32768          0     0  50000

  • Hi Woody,

    Let me try the RT SDK on my Beaglebone Black tomorrow and get back to you.