AM6442: DMASS maximum bandwidth doesn't match the maximum bandwidth of GPMC

Boshra

Part Number: AM6442

Hi,

I'm using an AM6442 HS-FS device, bare-metal on Windows, NO-RTOS.

I Just Passed through this ticket:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/994419/am6442-am64x-pktdma-buffers-and-burst-lengths/3687174?tisearch=e2e-sitesearch&keymatch=bcdma%2520priority#3687174

And it made me very worried. We were planning to use the UltraHigh capacity channel for BCDMA which is mentioned in the TRM of AM64x/AM243x to do block copies to/from an external FPGA through GPMC. But in the Above ticket, it mentions that AM64x doesn't support that. So then why is it mentioned in the TRM? Does AM243 support that?

The theoretical bandwidth for GPMC is 400 MBytes/sec. Now it seems that the maximum speed for BCDMA (considering 192 byte FIFO) is 96 MBytes/sec. Since GPMC has only one bus and can not handle more than one transfer, there is no possibility of breaking the transfer into 4 channels to use the 4 available BUSes for BCDMA. So BCDMA will be a bottleneck and there is no way to use the 400 MBytes/sec of the GPMC.

Is there any solution for our case?

Thanks,

Boshra

over 2 years ago

0 Pekka Varis over 2 years ago

TI__Mastermind 27050 points

Boshra said:
We were planning to use the UltraHigh capacity channel for BCDMA which is mentioned in the TRM of AM64x/AM243x to do block copies to/from an external FPGA through GPMC. But in the Above ticket, it mentions that AM64x doesn't support that. So then why is it mentioned in the TRM? Does AM243 support that?

The DMA section has the overview part that applies for multiple devices. Specific devices like AM6442 then specify their configuration in the details, in this case "11.2.1.5.2.21 DMASS0_BCDMA_0_CAP3 Register" has 0 in both "Tx ultra high capacity internal channel count" and "Tx high capacity internal channel count". This is the same in AM243x.

Boshra said:
The theoretical bandwidth for GPMC is 400 MBytes/sec.

Can you clarify how you got to this, or what is your configuration? 32-bit wide 100MHz ?

Boshra said:
Now it seems that the maximum speed for BCDMA (considering 192 byte FIFO) is 96 MBytes/sec

It is 192bytes in flight, so 192bytes divided by the latency to the memory. So assuming the latency from BCDMA through the interconnect and back to read a word from what you have connected to GPMC is 500ns, the bandwidth could be around 384MBytes/s (192bytes / 0x0000005s). 96MBytes/s comes from 2microsecond (0.000002s) latency.

0 Boshra over 2 years ago in reply to Pekka Varis

Intellectual 418 points

Hi,

Thank you so much for answering my tickets. I appreciate your time.

Pekka Varis said:
The DMA section has the overview part that applies for multiple devices. Specific devices like AM6442 then specify their configuration in the details, in this case "11.2.1.5.2.21 DMASS0_BCDMA_0_CAP3 Register" has 0 in both "Tx ultra high capacity internal channel count" and "Tx high capacity internal channel count". This is the same in AM243x.

I see. But in the TRM there is no explanation for this register field (and for many other registers their usage is not obvious). That's what I see and nowhere I can find the usage and explanation for this register. Do you have another document explaining them?

Pekka Varis said:
Can you clarify how you got to this, or what is your configuration? 32-bit wide 100MHz ?

Yes, that's the case.

Here is the configuration we have done for GPMC.

Register	Field	Value	Notes
GPMC_CONFIG	WAIT0PINPOLARITY	0h	WAIT active low
GPMC_CONFIG1_0	GPMCFCLKDIVIDER	0h
	TIMEPARAGRANULARITY	0h	Single clock
	MUXADDDATA	2h	Multiplexed AD
	DEVICETYPE	0h	NOR flash synchronous
	DEVICESIZE	2h	32-bit device
	WAITPINSELECT	0h	Use WAIT0
	WAITMONITORINGTIME	1h	WAIT active 1 clock cycle earlier
	WAITWRITEMONITORING	1h	Monitoring enabled for writes
	WAITREADMONITORING	1h	Monitoring enabled for reads
	ATTACHEDDEVICEPAGELENGTH	0h	Don’t care
	CLKACTIVATIONTIME	0h	No clock delay
	WRITETYPE	1h	Write synchronous
	WRITEMULTIPLE	0h	Single-access only
	READTYPE	1h	Read synchronous
	READMULTIPLE	0h	Single-access only
	WRAPBURST	0h	Don’t care
GPMC_CONFIG2_0/1	CSONTIME	0h	No CS delay
	CSEXTRADELAY	1h	Extend CS by half clock cycle
	CSRDOFFTIME	5h
	CSWROFFTIME	2h
GPMC_CONFIG3_0/1	ADVAADMUXWROFFTIME	0h	Don’t care
	ADVAADMUXRDOFFTIME	0h	Don’t care
	ADVWROFFTIME	1h	ADV off 1 cycle after CS
	ADVRDOFFTIME	1h	ADV off 1 cycle after CS
	ADVEXTRADELAY	0h	No extra delay
	ADVAADMUXONTIME	0h	Don’t care
	ADVAADMUXONTIME	0h	ADV on immediately
GPMC_CONFIG4_0/1	OEONTIME	2h	One clock OE delay
	OEAADMUX_ONTIME	0h	Don’t care
	OEEXTRADELAY	1h	One extra ½ clock delay
	OEOFFTIME	5h
	OEAADMUX_OFFTIME	0h	Don’t care
GPMC_CONFIG6_0/1	WRACCESSTIME	3h
	WRDATAONADMUXBUS	2h
	CYCLE2CYCLEDELAY	1h
	CYCLE2CYCLESAMECSEN	0h
	CYCLE2CYCLEDIFFCSEN	0h
	BUSTURNAROUND	0h
GPMC_CONFIG6_0/1	PAGEBURSTACCESSTIME	1h	Needs to be confirmed
	RDACCESSTIME	5h
	WRCYCLETIME	3h
	RDCYCLETIME	6h
GPMC_CONFIG1_1	GPMCFCLKDIVIDER	0h
	TIMEPARAGRANULARITY	0h
	MUXADDDATA	2h	Multiplexed AD
	DEVICETYPE	0h	NOR flash synchronous
	DEVICESIZE	2h	32-bit device
	WAITPINSELECT	0h	Use WAIT0
	WAITMONITORINGTIME	1h	WAIT active 1 clock cycle earlier
	WAITWRITEMONITORING	1h	Monitoring enabled for writes
	WAITREADMONITORING	1h	Monitoring enabled for reads
	ATTACHEDDEVICEPAGELENGTH	3h	32 words – To be confirmed
	CLKACTIVATIONTIME	0h	No clock delay
	WRITETYPE	1h	Burst access
	WRITEMULTIPLE	1h	Single-access only
	READTYPE	1h	Read synchronous
	READMULTIPLE	1h	Burst access
	WRAPBURST	0h	No wrap support

Pekka Varis said:
So assuming the latency from BCDMA through the interconnect and back to read a word from what you have connected to GPMC is 500ns

The GPMC is connected to an external FPGA and we want to do the bursts of 32 DoubleWord. And what we expect is to have a total latency of about 420ns.

Thanks,

Boshra

+1 Pekka Varis over 2 years ago in reply to Boshra

TI__Mastermind 27050 points

Boshra said:
And what we expect is to have a total latency of about 420ns.

with 192bytes in flight you should be able to see the 400Mbytes/s (192bytes / 0x00000042s).

Boshra said:
But in the TRM there is no explanation for this register field (and for many other registers their usage is not obvious). That's what I see and nowhere I can find the usage and explanation for this register. Do you have another document explaining them?

Unfortunately no, we recommend using the MCU+ SDK drivers (and Linux drivers) https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/latest/exports/docs/api_guide_am64x/DRIVERS_UDMA_PAGE.html as reference if you want to develop your own.

The CAP0 register, it is unused in AM64x. I agree it is a little weird to list it with a name and all bits reserved, but it is accurate. That address is a reserved area.

0 Boshra over 2 years ago in reply to Pekka Varis

Intellectual 418 points

Hi,

Do you mind taking a look at my other ticket as well, please?

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1270918/am6442-how-to-have-a-burst-instead-of-single-reads-writes-in-dmass?tisearch=e2e-sitesearch&keymatch=%2520user%253A563969#

Thanks,
Boshra

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AM6442: DMASS maximum bandwidth doesn't match the maximum bandwidth of GPMC