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AM6442: How to modify the DDR driver to adapt to the external DDR chip of the custom board

wen f
Prodigy 245 points
Part Number: AM6442
Other Parts Discussed in Thread: SYSCONFIG,

Hello TI technical experts，

SDK version: mcu_plus_sdk_am64x_08_06_00_45

Chip model: AM6442BSEFHAALV 2APONES 709 (HS-FS device)

I'm having trouble debugging the DDR memory on my custom board, the DDR chip is: K4A8G165WC

I want to know how to modify the DDR driver to adapt to the DDR chip on my custom board. Does TI have guidance documents like custom flash to help me modify the DDR driver? If not, how should I start modifying which part of the DRR driver code?

Best Regards

Wen

  • 0
    TI__Guru* 85820 points

    Wen, you need to use the DDR Register Configuration Tool in Sysconfig: https://dev.ti.com/sysconfig/?product=Processor_DDR_Config&device=AM64x

    to generate a register configuration for your board, and then build that configuration into your code.  Please check the README in the tool for instructions.  Further instructions specific to the MCU+ SDK are here:  https://software-dl.ti.com/mcu-plus-sdk/esd/AM64X/09_00_00_35/exports/docs/api_guide_am64x/DRIVERS_DDR_PAGE.html

    If you have further questions, you can ask here

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 245 points

    Hi James，

    I have used the tools you recommended to configure the timing parameters, but after testing, I still cannot get the DDR4 on my custom board to work properly.

    The following are the specific parameters I configured and the DDR chip model for your reference:

    1. DDR chip：K4A8G165WC-BIWE，Datasheet is here：K4A8G165WC-BIWE.pdf

    2. The timing parameters are as follows:

    DRAM Timing A 　 Notes
    CL（nCK）[CAS Latency] 11
    CWL（nCK）[CAS Write Latency] 9
    DRAM Timing B 　
    tXPR (tCK) 5
    tPW_RESET_L (ns) 1000
    tRFC (ns) 350
    tREFI (ns) 7800
    tDQSCK min (ns) 0.225 The DDR data sheet is -0.225
    tDQSCK max (ns) 0.225
    tDLLK (tCK) 597
    tRCD (ns) 13.75
    tRP (ns) 13.75
    tRAS (ns) 35
    tRRD_S (tCK) 4
    tRRD_S (ns) 6
    tRRD_L (tCK) 4
    tRRD_L (ns) 7.5
    tFAW (tCK) 28
    tFAW (ns) 35
    tWR (ns) 15
    tWR_CRC_DM (tCK) 4
    tWR_CRC_DM (ns) 3.75
    tWTR_S (tCK) 2
    tWTR_S (ns) 2.5
    tWTR_L (tCK) 4（6） There are two different values ​​written on the DDR data sheet
    tWTR_L (ns) 7.5
    tWTR_S_CRC_DM (tCK) 4
    tWTR_S_CRC_DM (ns) 3.75
    tRTP (tCK) 4
    tRTP (ns) 7.5
    tCCD_S (tCK) 4
    tCCD_L (tCK) 5
    tCCD_L (ns) 6.25
    tMRD (tCK) 8
    tMOD (tCK) 24
    tMOD (ns) 15
    tCKSRE (tCK) 5
    tCKSRE (ns) 10
    tCKSRX (tCK) 5
    tCKSRX (ns) 10
    tXP (tCK) 4
    tXP (ns) 6
    tCKE (tCK) 3
    tCKE (ns) 5
    ODTH8 (tCK) 6 This parameter is not written in the DDR data sheet
    tPAR_ALERT_PW max (tCK) 96

    IOControl A
    Processor / DDR Controller IO Configuration    		 　 The meaning of these values is not clear，Use default values from TI tools
    VREF Control Range DQ/DM Range 1
    VREF Control Range DQ/DM 72.8
    Driver Impedance for DQ/DQS/DM 40 Ohm
    Driver Impedance for Addr/Ctrl/Clk 40 Ohm
    ODT for DQ/DQS/DM 48 Ohm
    IOControl B
    DRAM IO Configuration    		 　
    DQ VREF Range Range 1
    DQ VREF 72.4
    Output Driver Impedance (ODI) RZQ/7(34ohm)
    Nominal ODT (RttNOM) RZQ/6(40ohm)
    Dynamic ODT Disabled

    There are too many timing parameters in this table, I am not sure if all these parameter values are required, or some parameters are required and some parameters are optional? And I didn't find any description about the DDR16SS0_CTL_CFG register in the latest AM6442 TRM, so now it is very difficult for me to adapt this DDR chip to my custom board.

    Best Regards

    Wen

  • +1 in reply to wen f
    TI__Guru* 85820 points

    For DQSCKmin, keep the value of .225.  This is taken as a negative value

    For tWTR_L, you should be taking values from table57 (column DDR4-3200 since you have that speed grade device), so this should be 4tCK

    For ODTH8, keep the default value if it is not shown in the datasheet.  

    How are you testing this?  Are you rebuilding the new configuration into the MCU+ SDK then trying to boot?  Are you able to connect to JTAG with Code Composer?  It might be easier to debug this via JTAG.

    Regards,

    James