Hello,TI:
I tried to set 0xA4700800~0xA500800 NOCACHE in mpu_init. but During debugging, it is found that the actual effective address is 0xA4100000~0xA480000
.regionId = 13U,
.enable = 1U,
.baseAddr = 0xA4700800,
.size = CSL_ARM_R5_MPU_REGION_SIZE_8MB,
.subRegionEnable = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
.exeNeverControl = 0U,
.accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
.shareable = 1U,
.cacheable = (uint32_t)FALSE,
.cachePolicy = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,
.memAttr = CSL_ARM_R5_MEM_ATTR_STRONGLY_ORDERED,
so I want to know what is the relationship between cache rules and physical address blocks?
BR
Li Ping
