Questions on C6678 EVM board

I merged all three questions into one thread as they're all EVM related.

Note this is Advantech's board design.  The design was created prior to our Design Guidelines being completed.  You may find items which do not follow our Design Guidelines.  You should make sure to follow our design guidelines.

Wenjun Huang said:

On p32 of C6678 EVM board, there is the boundary scan when BSC_EN#=0.

Why is only PHY (representing 88E1111 Gigabit Ethernet transceiver), 9222 and FPGA in the boundary scan loop. Why not the other chips like DSP core, Mixed Signal Controller, etc.?

BSC_JTAG_TCK-->FPGA_JTAG_TCK in the table "When DSC_EN#=0" cell should not be mentioned as it has already been mentioned in "Always enabling :" cell. For "When BSC_EN# = 1:" cell, it also did not mention BSC_JTAG_TCK-->FPGA_JTAG_TCK.

Also in the "When DSC_EN#=0" cell, there is a entry left out which is shown in the TI_SN74ALVC244PWR chip U7 2A1 -> 2Y1. BSC_JTAG_TMS -> FPGA_JTAG_TMS.

The DSP is implement w/ a separate JTAG interface, and boundary scan for the DSP is done through that JTAG interface.  

This is only speculation, but I'd assume they did it this way so they can check the other major components of the board w/o the DSP powered up to ensure everything is fine prior to powering up the DSP.  You'd have to ask Advantech themselves as to why they did this.

Best Regards,

Chad

Wenjun Huang said:

p34 of C6678 EVM Board

Why is there 2 chips to provide 1.8V? Is it to provide more current as 1 chip can provide 0.5A whereas another chip can provide 0.3A, adding to a total of 0.8A.

However, the TPS73701 chip can provide up to 1A, from its datasheet.

The  VCC1V8_AUX rail is for the Xilinx FPGA, which controls the boot and power sequencing of the DSP on the board (The 1.2 and 3.3v rails are also connected to the Xilinx and other components but not the DSP.)  Since the FPGA is used to drive bootmode pins and power sequence of the DSP power supplies it must be on prior to the 1.8V rail of the DSP being powered up.

Best Regards,

Chad

Wenjun Huang said:

On p20 of C6678 EVM board document,

for VDDR1 - 4, there is just one pin for each of VDDRx. Why is there the need to use 4 capacitor (eg. C477, C478, C479, C480) arranged in parallel. Could it be replaced by 1 capacitor (value = sum of all the capacitors used) which will reduce the space on the PCB. Is it because no just capacitor exist, or for other reason?

I believe they are building LC circuits (remember traces are inductive) w/ the bypass portion of the caps to suppress noise.  The VDDRx pins are regulator supplies for the SerDes interfaces and thus you'd want the levels seen to be as noise free as possible.  I'm not a board designer myself, but I think this is common practice.  I'll check with a board designer to confirm this and reply back.