TDA4VE-Q1: Multiple GPIO input interrupts

gg yang

Expert 1190 points

Part Number: TDA4VE-Q1

Hi .

SDK0806

1. When only # define GPIO_ BANK1

has 2 GPIOs that can generate independent interrupts.

2 .When only # define GPIO0_ 2_5

GPIO0_2 GPIO2_5 can generate independent interrupts.

3 .When only #define GPIO0_49_50

gpio0_ 49 gpio0_ 50 can generate independent interrupts.

4. When

#define GPIO0_49_50

#define GPIO0_2_5

#define GPIO_BANK1

only has GPIO0_ 49 GPIO0_ 50 can generate independent interrupts

Fullscreen gpio_int.c Download

#include <utils/console_io/include/app_log.h>
#include <ti/csl/arch/csl_arch.h>
#include <ti/csl/soc.h>
#include <ti/csl/cslr.h>
#include <ti/osal/osal.h>
#include <ti/osal/TaskP.h>
#include <ti/board/src/j721s2_evm/include/board_internal.h>
#include <ti/board/src/j721s2_evm/J721S2_pinmux.h>
#include <string.h>
#include <ti/csl/csl_utils.h>
#include <ti/csl/soc/j721s2/src/cslr_soc.h>
#include <ti/csl/csl_types.h>
#include <ti/csl/hw_types.h>
#include <ti/csl/soc.h>
#include <ti/csl/arch/csl_arch.h>
#include <ti/drv/gpio/soc/GPIO_soc.h>
#include <ti/drv/sciclient/sciclient.h>
#include <ti/csl/csl_clec.h>



typedef unsigned  int	uintptr_t;
typedef unsigned int    uint32;
//#define GPIO_PIN_NUM  2 //49   //GPIO0_51
//#define GPIO_PIN_NUM  51   //GPIO0_51
#define GPIO_17_PIN_NUM  17   //GPIO0_17    
#define GPIO_23_PIN_NUM  23   //GPIO0_23
#define GPIO_19_PIN_NUM  19   //GPIO0_19
#define GPIO_50_PIN_NUM  50   //GPIO0_50
#define GPIO_5_PIN_NUM  5     //GPIO0_5
#define GPIO_26_PIN_NUM  26   //GPIO0_26
#define GPIO_24_PIN_NUM  24   //GPIO0_24
#define GPIO_49_PIN_NUM  49   //GPIO0_28
#define GPIO_28_PIN_NUM  28   //GPIO0_28
#define GPIO_30_PIN_NUM  30   //GPIO0_30
#define GPIO_31_PIN_NUM  31   //GPIO0_31
#define GPIO_2_PIN_NUM  2   //GPIO0_2

//uint32_t INTR_OFFSET = 8u;
uint32_t INTR_OFFSET = 0u;

//#define GPIOMUX_INTRTR0_OUTP_START_R5FSS0 (16u + INTR_OFFSET)
#define GPIOMUX_INTRTR0_OUTP_START_R5FSS0 (16 + INTR_OFFSET)

#define GPIO_START            (37)


#define GPIO0_2_5
#define GPIO_BANK1			
#define GPIO0_49_50

#ifdef GPIO_BANK1
#define APP_NUM_CH  2
#endif
#ifdef GPIO0_2_5
#define APP_NUM_CH  2
#endif 
#ifdef GPIO0_49_50
#define APP_NUM_CH  2
#endif
 

#if defined(GPIO_BANK1) && defined(GPIO0_2_5) 
#define APP_NUM_CH  4
#endif 

#if defined(GPIO_BANK1) && defined(GPIO0_49_50) 
#define APP_NUM_CH  4
#endif 
#if defined(GPIO0_2_5) && defined(GPIO0_49_50) 
#define APP_NUM_CH  4
#endif

#if defined(GPIO_BANK1) && defined(GPIO0_2_5)  && defined(GPIO0_49_50) 
#define APP_NUM_CH  6
#endif

#define FLS_I 2 
#define RLC_I 5  
 
#define RRS_I 17 // // GPIO0_17
#define RRM_I 19 //

#define FRC_I 49 
#define RLM_I 50 
 

static volatile uint32_t gIntAggrLeviEvtId[16] = {
        116, 117, 118, 119, 120, 121, 122, 123,
        124, 125, 126, 127, 128, 129, 130, 131};
static uint8_t gpio_input[APP_NUM_CH] = {
	
#ifdef GPIO0_2_5
	FLS_I, RLC_I,
#endif 

#ifdef GPIO_BANK1	
    RRS_I,  RRM_I,
#endif	
#ifdef  GPIO0_49_50
	FRC_I,  RLM_I,
#endif 	

};




void gpio_callback_isr_2(uintptr_t arg)
{
    appLogPrintf(" interrupt...GPIO_PIN_NUM %d\n",GPIO_2_PIN_NUM);
}

void gpio_callback_isr_5(uintptr_t arg)
{
    appLogPrintf(" interrupt...GPIO_PIN_NUM %d\n",GPIO_5_PIN_NUM);
}

void gpio_callback_isr_17(uintptr_t arg)
{
    appLogPrintf(" interrupt...GPIO_PIN_NUM %d\n",GPIO_17_PIN_NUM);
}
void gpio_callback_isr_19(uintptr_t arg)
{
    appLogPrintf(" interrupt...GPIO_PIN_NUM %d\n",GPIO_19_PIN_NUM);
}
void gpio_callback_isr_49(uintptr_t arg)
{
    appLogPrintf(" interrupt...GPIO_PIN_NUM %d\n",GPIO_49_PIN_NUM);
}

void gpio_callback_isr_50(uintptr_t arg)
{
    appLogPrintf(" interrupt...GPIO_PIN_NUM %d\n",GPIO_50_PIN_NUM);
}



 
static void gpio_pinmux(void)
{
	uint32 regVal = 0U;
	/* Pinmux for  GPIO0_51 */
	// regVal = (PIN_MODE(7U) | ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & PIN_INPUT_ENABLE)));
	regVal = 0x50007;

    HW_WR_REG32(0x11c008, regVal);   //AC24 gpio0—2	
	HW_WR_REG32(0x11c014, regVal);   //AD25 gpio0—5   
	
	HW_WR_REG32(0x11c044, regVal);   //Y26  gpio0—17     
	HW_WR_REG32(0x11c04c, regVal);   //V26  gpio0—19
	
    HW_WR_REG32(0x11c0C4, regVal);   //AB26 gpio0—49 	
	HW_WR_REG32(0x11c0C8, regVal);   //AD28 gpio0—50 
    
	
    
}

static void initGpioisIntrrput(uint32_t gpio_id)
{
    uint32_t chIdx, bitpos, bank_id;
    bitpos = gpio_id % 32;
    bank_id = gpio_id / 16;

    // *(volatile uint32_t *)0x00600044 = (1u << bitpos);
    // *(volatile uint32_t *)0x00600038 &= ~(1u << bitpos);
   if(bank_id<2)
   {
		*(volatile uint32_t *)0x00600024 = (1u << bitpos);   // Writing 1 clears rising edge detection for GPIO bank 3 or 2 bits
		*(volatile uint32_t *)0x0060002c = (1u << bitpos);   // Writing 1 enables falling edge detection for for GPIO bank 3 or 2 bits

		*(volatile uint32_t *)0x00600034 = (1u << bitpos);

		// *(volatile uint32_t *)0x00600044 = (1u << bitpos);
		// *(volatile uint32_t *)0x00600038 &= ~(1u << bitpos);

		*(volatile uint32_t *)0x00600008 = (1u << bank_id);
	}
	else
	{
		*(volatile uint32_t *)0x0060004C = (1u << bitpos);   // Writing 1 clears rising edge detection for GPIO bank 3 or 2 bits
		*(volatile uint32_t *)0x00600054 = (1u << bitpos);   // Writing 1 enables falling edge detection for for GPIO bank 3 or 2 bits

		*(volatile uint32_t *)0x0060005C = (1u << bitpos);

		// *(volatile uint32_t *)0x00600044 = (1u << bitpos);
		// *(volatile uint32_t *)0x00600038 &= ~(1u << bitpos);

		*(volatile uint32_t *)0x00600008 = (1u << bank_id);

    // *(volatile uint32_t *)0x0060004C = (1u << bitpos);
    // *(volatile uint32_t *)0x00600054 = (1u << bitpos);
	}
}

 
static void App_setupGpioMuxIr()
{
    int32_t                             status;
    uint32_t                            chIdx;
    struct tisci_msg_rm_irq_set_req     rmIrqReq;
    struct tisci_msg_rm_irq_set_resp    rmIrqResp;
    //int32_t i;

    memset(&rmIrqReq, 0x0, sizeof(rmIrqReq));
    memset(&rmIrqResp, 0x0, sizeof(rmIrqResp));

    rmIrqReq.valid_params           = 0U;
    rmIrqReq.global_event           = 0U;
    rmIrqReq.src_id                 = 0U;
    rmIrqReq.src_index              = 0U;
    rmIrqReq.dst_id                 = 0U;
    rmIrqReq.dst_host_irq           = 0U;
    rmIrqReq.ia_id                  = 0U;
    rmIrqReq.vint                   = 0U;
    rmIrqReq.vint_status_bit_index  = 0U;
    rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        rmIrqReq.src_id         = TISCI_DEV_GPIOMUX_INTRTR0;
        //rmIrqReq.src_index      = GPIO_START + chIdx;
        rmIrqReq.src_index      = gpio_input[chIdx];

        /* Set the destination based on the core */
        rmIrqReq.dst_id         = TISCI_DEV_GPIOMUX_INTRTR0;
        rmIrqReq.dst_host_irq   = GPIOMUX_INTRTR0_OUTP_START_R5FSS0 + chIdx;
  

        /* Set the destination interrupt */
        rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
        rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
		
        appLogPrintf("gpio_int [%s:%d] src_id=%d\n",__func__, __LINE__,rmIrqReq.src_id);
        appLogPrintf("gpio_int [%s:%d] src_index=%d\n",__func__, __LINE__,rmIrqReq.src_index);
        appLogPrintf("gpio_int [%s:%d] dst_id=%d\n",__func__, __LINE__,rmIrqReq.dst_id);
    
        appLogPrintf("dst_host_irq=%d \n", rmIrqReq.dst_host_irq);
        status = Sciclient_rmIrqSetRaw(
                (const struct tisci_msg_rm_irq_set_req *)&rmIrqReq,
                &rmIrqResp,
                SCICLIENT_SERVICE_WAIT_FOREVER);

        if(status == CSL_PASS)
        {
            appLogPrintf ("Sciclient_rmIrqSetRaw Worked fine \n");
        }
        else
        {
            appLogPrintf("Sciclient_rmIrqSetRaw Failed :%d\n", status);
        }
    }
}

void register_isr_fun(int intNum,Osal_IsrRoutine routine)
{
    OsalRegisterIntrParams_t    intrPrms;
    HwiP_Handle hwiHandle;
    OsalInterruptRetCode_e      osalRetVal;

    Osal_RegisterInterrupt_initParams(&intrPrms);
    intrPrms.corepacConfig.arg          = (uintptr_t)NULL;
    intrPrms.corepacConfig.isrRoutine   = routine;
    intrPrms.corepacConfig.priority     = 1U;
    intrPrms.corepacConfig.corepacEventNum = 0U; /* NOT USED ? */
    intrPrms.corepacConfig.intVecNum        = intNum;

    osalRetVal = Osal_RegisterInterrupt(&intrPrms, &hwiHandle);
    appLogPrintf("[%s:%d] Osal_RegisterInterrupt intNum=%d osalRetVal=%d\n",__func__, __LINE__,intNum,osalRetVal);
    if(OSAL_INT_SUCCESS != osalRetVal)
    {
         appLogPrintf ("Osal_RegisterInterrupt fail \n");
    }else{
         appLogPrintf ("Osal_RegisterInterrupt fine \n");
    }
}
void initAllGpioisIntrrput(void)
{

#ifdef  GPIO0_2_5
	initGpioisIntrrput(GPIO_5_PIN_NUM);
	initGpioisIntrrput(GPIO_2_PIN_NUM);
#endif 

#ifdef GPIO_BANK1
	initGpioisIntrrput(GPIO_17_PIN_NUM);
	initGpioisIntrrput(GPIO_19_PIN_NUM);
#endif 


#ifdef  GPIO0_49_50
 	initGpioisIntrrput(GPIO_49_PIN_NUM);
 	initGpioisIntrrput(GPIO_50_PIN_NUM);
#endif 

}


void mcu30test_gpio_interrupt(void)
{
  //  int32_t i = 0; 
    gpio_pinmux();
    initAllGpioisIntrrput();
 	App_setupGpioMuxIr();



#if defined(GPIO_BANK1) && defined(GPIO0_2_5)  && defined(GPIO0_49_50) 
    appLogPrintf ("GPIO0_2_5 17 19 49 50 \n");
	register_isr_fun(176,&gpio_callback_isr_2);  
    register_isr_fun(177,&gpio_callback_isr_5); 
	 
    register_isr_fun(178,&gpio_callback_isr_17);
	register_isr_fun(179,&gpio_callback_isr_19); 

	register_isr_fun(180,&gpio_callback_isr_49);  
	register_isr_fun(181,&gpio_callback_isr_50); 
#elif  defined(GPIO0_2_5)
	register_isr_fun(176,&gpio_callback_isr_2);  
    register_isr_fun(177,&gpio_callback_isr_5); 
	
#elif defined(GPIO_BANK1)  
    appLogPrintf ("GPIO0_17 19 \n");
	register_isr_fun(176,&gpio_callback_isr_17);  
	register_isr_fun(177,&gpio_callback_isr_19); 
	
#elif  defined(GPIO0_49_50) 
    appLogPrintf ("GPIO0_49_50 \n");
	register_isr_fun(176,&gpio_callback_isr_49);  
	register_isr_fun(177,&gpio_callback_isr_50); 
#endif
  
}

over 2 years ago

0 Brijesh Jadav over 1 year ago

TI__Guru**** 475345 points

Hi gj y,

I am bit confused here. Do you want to setup Bank GPIO interrupt or individual GPIO interrupt? In the code, the API App_setupGpioMuxIr sets up the individual GPIO interrupt.

Also have you changed resource manager to allocate more GPIO interrupt to this R5F? You can allocate 12 or at max 16 GPIO interrupt to this R5F and can register interrupts for individual GPIOs.. This is one way to get the GPIO interrupts.

Regards,

Brijesh

0 gg yang over 1 year ago in reply to Brijesh Jadav

Expert 1190 points

Hi Brijesh

I need independent GPIO interrupts. I have changed the resource manager and have allocated 12 interrupts in r5f.

I don't know why all of these are opened but cannot be used?

1. When only # define GPIO_ BANK1

When gpio0_ 17 Rising or falling edge it can enter gpio0_ 17 interrupt handling function,

When Gpio0_ 23 Rising or falling edge, it can enter gpio0_ 23 interrupt handling function,

When only # define GPIO0_ 2_5

When gpio0_ 2 or gpio0_5 Rising or falling edge It can also enter its interrupt processing function.

#define GPIO0_49_50

When only # define GPIO0_49_50

When gpio0_ 49 or gpio0_50 Rising or falling edge It can also enter gpio0_ 49 or gpio0_ 50 iinterrupt processing function.

.When

#define GPIO0_49_50

#define GPIO0_2_5

#define GPIO_BANK1

only has GPIO0_ 49 and GPIO0_ 50 Rising or falling edge, it can enter gpio0_ 49 or gpio0_ 50 interrupt handling function,

Other gpio Rising or falling edges cannot enter any interrupt handling functions.

Regards,

0 Brijesh Jadav over 1 year ago in reply to gg yang

TI__Guru**** 475345 points

Hi gj y,

When you generate interrupt on all of these GPIOs, do you see these bits getting set in GPIO_INT_STAT register?

I dont understand why you are registering same irq number for multiple GPIO interrupt. Once you allocate 12 GPIO output interrupts to this R5F, it will generate interrupt on a separate Irq number, so you should register separate ISR for each of these 12 Irqs.

#elif defined(GPIO0_2_5)
register_isr_fun(176,&gpio_callback_isr_2);
register_isr_fun(177,&gpio_callback_isr_5);

#elif defined(GPIO_BANK1)
appLogPrintf ("GPIO0_17 19 \n");
register_isr_fun(176,&gpio_callback_isr_17);
register_isr_fun(177,&gpio_callback_isr_19);

#elif defined(GPIO0_49_50)
appLogPrintf ("GPIO0_49_50 \n");
register_isr_fun(176,&gpio_callback_isr_49);
register_isr_fun(177,&gpio_callback_isr_50);
#endif

Also please make sure to select pinmux for all 12 GPIO pins, in the code, i see pinmux setting only for 6 pins.

HW_WR_REG32(0x11c008, regVal); //AC24 gpio0—2
HW_WR_REG32(0x11c014, regVal); //AD25 gpio0—5

HW_WR_REG32(0x11c044, regVal); //Y26 gpio0—17
HW_WR_REG32(0x11c04c, regVal); //V26 gpio0—19

HW_WR_REG32(0x11c0C4, regVal); //AB26 gpio0—49
HW_WR_REG32(0x11c0C8, regVal); //AD28 gpio0—50

Regards,

Brijesh

0 gg yang over 1 year ago in reply to Brijesh Jadav

Expert 1190 points

Hi Brijesh

1.The value of GPIO_INT_STAT register (0x600034 or 0x60005c) is 0.

2.Because there are macro definitions, Not using multiple GPIOs to register the same interrupt number at the same time

#elif defined(GPIO0_2_5)
register_isr_fun(176,&gpio_callback_isr_2);
register_isr_fun(177,&gpio_callback_isr_5);

#elif defined(GPIO_BANK1)
appLogPrintf ("GPIO0_17 19 \n");
register_isr_fun(176,&gpio_callback_isr_17);
register_isr_fun(177,&gpio_callback_isr_19);

#elif defined(GPIO0_49_50)
appLogPrintf ("GPIO0_49_50 \n");
register_isr_fun(176,&gpio_callback_isr_49);
register_isr_fun(177,&gpio_callback_isr_50);
#endif

To avoid misunderstandings, I made code changes

Fullscreen 3482.gpio_int.c Download

#include <utils/console_io/include/app_log.h>
#include <ti/csl/arch/csl_arch.h>
#include <ti/csl/soc.h>
#include <ti/csl/cslr.h>
#include <ti/osal/osal.h>
#include <ti/osal/TaskP.h>
#include <ti/board/src/j721s2_evm/include/board_internal.h>
#include <ti/board/src/j721s2_evm/J721S2_pinmux.h>
#include <string.h>
#include <ti/csl/csl_utils.h>
#include <ti/csl/soc/j721s2/src/cslr_soc.h>
#include <ti/csl/csl_types.h>
#include <ti/csl/hw_types.h>
#include <ti/csl/soc.h>
#include <ti/csl/arch/csl_arch.h>
#include <ti/drv/gpio/soc/GPIO_soc.h>
#include <ti/drv/sciclient/sciclient.h>
#include <ti/csl/csl_clec.h>



typedef unsigned  int	uintptr_t;
typedef unsigned int    uint32;
//#define GPIO_PIN_NUM  2 //49   //GPIO0_51
//#define GPIO_PIN_NUM  51   //GPIO0_51
#define GPIO_17_PIN_NUM  17   //GPIO0_17    
#define GPIO_23_PIN_NUM  23   //GPIO0_23
#define GPIO_19_PIN_NUM  19   //GPIO0_19
#define GPIO_50_PIN_NUM  50   //GPIO0_50
#define GPIO_5_PIN_NUM  5     //GPIO0_5
#define GPIO_26_PIN_NUM  26   //GPIO0_26
#define GPIO_24_PIN_NUM  24   //GPIO0_24
#define GPIO_49_PIN_NUM  49   //GPIO0_28
#define GPIO_28_PIN_NUM  28   //GPIO0_28
#define GPIO_30_PIN_NUM  30   //GPIO0_30
#define GPIO_31_PIN_NUM  31   //GPIO0_31
#define GPIO_2_PIN_NUM  2   //GPIO0_2



#define GPIO_START            (37)


#define GPIO0_2_5
#define GPIO_BANK1			
#define GPIO0_49_50


#ifdef GPIO0_2_5
#define APP_NUM_CH  2
#define  INTR_OFFSET   0
#endif 

#ifdef GPIO_BANK1
#define APP_NUM_CH  2
#define  INTR_OFFSET   2 
#endif

#ifdef GPIO0_49_50
#define APP_NUM_CH  2
#define  INTR_OFFSET   4 
#endif
 

#if defined(GPIO_BANK1) && defined(GPIO0_2_5) 
#define APP_NUM_CH  4
#define  INTR_OFFSET   0
#endif 

#if defined(GPIO_BANK1) && defined(GPIO0_49_50) 
#define APP_NUM_CH  4
#define  INTR_OFFSET   2
 
#endif 
#if defined(GPIO0_2_5) && defined(GPIO0_49_50) 
#define APP_NUM_CH  4
#endif

#if defined(GPIO_BANK1) && defined(GPIO0_2_5)  && defined(GPIO0_49_50) 
#define APP_NUM_CH  6
#define  INTR_OFFSET   0
#endif

#define FLS_I 2 
#define RLC_I 5  
 
#define RRS_I 17 // // GPIO0_17
#define RRM_I 19 //

#define FRC_I 49 
#define RLM_I 50 
 
//uint32_t INTR_OFFSET = 8u;
 

//#define GPIOMUX_INTRTR0_OUTP_START_R5FSS0 (16u + INTR_OFFSET)
#define GPIOMUX_INTRTR0_OUTP_START_R5FSS0 (16 + INTR_OFFSET)
static volatile uint32_t gIntAggrLeviEvtId[16] = {
        116, 117, 118, 119, 120, 121, 122, 123,
        124, 125, 126, 127, 128, 129, 130, 131};
static uint8_t gpio_input[APP_NUM_CH] = {
	
#ifdef GPIO0_2_5
	FLS_I, RLC_I,
#endif 

#ifdef GPIO_BANK1	
    RRS_I,  RRM_I,
#endif	
#ifdef  GPIO0_49_50
	FRC_I,  RLM_I,
#endif 	

};




void gpio_callback_isr_2(uintptr_t arg)
{
    appLogPrintf(" interrupt...GPIO_PIN_NUM %d\n",GPIO_2_PIN_NUM);
}

void gpio_callback_isr_5(uintptr_t arg)
{
    appLogPrintf(" interrupt...GPIO_PIN_NUM %d\n",GPIO_5_PIN_NUM);
}

void gpio_callback_isr_17(uintptr_t arg)
{
    appLogPrintf(" interrupt...GPIO_PIN_NUM %d\n",GPIO_17_PIN_NUM);
}
void gpio_callback_isr_19(uintptr_t arg)
{
    appLogPrintf(" interrupt...GPIO_PIN_NUM %d\n",GPIO_19_PIN_NUM);
}
void gpio_callback_isr_49(uintptr_t arg)
{
    appLogPrintf(" interrupt...GPIO_PIN_NUM %d\n",GPIO_49_PIN_NUM);
}

void gpio_callback_isr_50(uintptr_t arg)
{
    appLogPrintf(" interrupt...GPIO_PIN_NUM %d\n",GPIO_50_PIN_NUM);
}



 
static void gpio_pinmux(void)
{
	uint32 regVal = 0U;
	/* Pinmux for  GPIO0_51 */
	// regVal = (PIN_MODE(7U) | ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & PIN_INPUT_ENABLE)));
	regVal = 0x50007;

    HW_WR_REG32(0x11c008, regVal);   //AC24 gpio0—2	
	HW_WR_REG32(0x11c014, regVal);   //AD25 gpio0—5   
	
	HW_WR_REG32(0x11c044, regVal);   //Y26  gpio0—17     
	HW_WR_REG32(0x11c04c, regVal);   //V26  gpio0—19
	
    HW_WR_REG32(0x11c0C4, regVal);   //AB26 gpio0—49 	
	HW_WR_REG32(0x11c0C8, regVal);   //AD28 gpio0—50 
    
	
    
}

static void initGpioisIntrrput(uint32_t gpio_id)
{
    uint32_t chIdx, bitpos, bank_id;
    bitpos = gpio_id % 32;
    bank_id = gpio_id / 16;

    // *(volatile uint32_t *)0x00600044 = (1u << bitpos);
    // *(volatile uint32_t *)0x00600038 &= ~(1u << bitpos);
   if(bank_id<2)
   {
		*(volatile uint32_t *)0x00600024 = (1u << bitpos);   // Writing 1 clears rising edge detection for GPIO bank 3 or 2 bits
		*(volatile uint32_t *)0x0060002c = (1u << bitpos);   // Writing 1 enables falling edge detection for for GPIO bank 3 or 2 bits

		*(volatile uint32_t *)0x00600034 = (1u << bitpos);

		// *(volatile uint32_t *)0x00600044 = (1u << bitpos);
		// *(volatile uint32_t *)0x00600038 &= ~(1u << bitpos);

		*(volatile uint32_t *)0x00600008 = (1u << bank_id);
	}
	else
	{
		*(volatile uint32_t *)0x0060004C = (1u << bitpos);   // Writing 1 clears rising edge detection for GPIO bank 3 or 2 bits
		*(volatile uint32_t *)0x00600054 = (1u << bitpos);   // Writing 1 enables falling edge detection for for GPIO bank 3 or 2 bits

		*(volatile uint32_t *)0x0060005C = (1u << bitpos);

		// *(volatile uint32_t *)0x00600044 = (1u << bitpos);
		// *(volatile uint32_t *)0x00600038 &= ~(1u << bitpos);

		*(volatile uint32_t *)0x00600008 = (1u << bank_id);

    // *(volatile uint32_t *)0x0060004C = (1u << bitpos);
    // *(volatile uint32_t *)0x00600054 = (1u << bitpos);
	}
}

 
static void App_setupGpioMuxIr()
{
    int32_t                             status;
    uint32_t                            chIdx;
    struct tisci_msg_rm_irq_set_req     rmIrqReq;
    struct tisci_msg_rm_irq_set_resp    rmIrqResp;
    //int32_t i;

    memset(&rmIrqReq, 0x0, sizeof(rmIrqReq));
    memset(&rmIrqResp, 0x0, sizeof(rmIrqResp));

    rmIrqReq.valid_params           = 0U;
    rmIrqReq.global_event           = 0U;
    rmIrqReq.src_id                 = 0U;
    rmIrqReq.src_index              = 0U;
    rmIrqReq.dst_id                 = 0U;
    rmIrqReq.dst_host_irq           = 0U;
    rmIrqReq.ia_id                  = 0U;
    rmIrqReq.vint                   = 0U;
    rmIrqReq.vint_status_bit_index  = 0U;
    rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    rmIrqReq.secondary_host         = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;

    for(chIdx = 0U; chIdx < APP_NUM_CH; chIdx++)
    {
        rmIrqReq.src_id         = TISCI_DEV_GPIOMUX_INTRTR0;
        //rmIrqReq.src_index      = GPIO_START + chIdx;
        rmIrqReq.src_index      = gpio_input[chIdx];

        /* Set the destination based on the core */
        rmIrqReq.dst_id         = TISCI_DEV_GPIOMUX_INTRTR0;
        rmIrqReq.dst_host_irq   = GPIOMUX_INTRTR0_OUTP_START_R5FSS0 + chIdx;
  

        /* Set the destination interrupt */
        rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
        rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
		
        appLogPrintf("gpio_int [%s:%d] src_id=%d\n",__func__, __LINE__,rmIrqReq.src_id);
        appLogPrintf("gpio_int [%s:%d] src_index=%d\n",__func__, __LINE__,rmIrqReq.src_index);
        appLogPrintf("gpio_int [%s:%d] dst_id=%d\n",__func__, __LINE__,rmIrqReq.dst_id);
    
        appLogPrintf("dst_host_irq=%d \n", rmIrqReq.dst_host_irq);
        status = Sciclient_rmIrqSetRaw(
                (const struct tisci_msg_rm_irq_set_req *)&rmIrqReq,
                &rmIrqResp,
                SCICLIENT_SERVICE_WAIT_FOREVER);

        if(status == CSL_PASS)
        {
            appLogPrintf ("Sciclient_rmIrqSetRaw Worked fine \n");
        }
        else
        {
            appLogPrintf("Sciclient_rmIrqSetRaw Failed :%d\n", status);
        }
    }
}

void register_isr_fun(int intNum,Osal_IsrRoutine routine)
{
    OsalRegisterIntrParams_t    intrPrms;
    HwiP_Handle hwiHandle;
    OsalInterruptRetCode_e      osalRetVal;

    Osal_RegisterInterrupt_initParams(&intrPrms);
    intrPrms.corepacConfig.arg          = (uintptr_t)NULL;
    intrPrms.corepacConfig.isrRoutine   = routine;
    intrPrms.corepacConfig.priority     = 1U;
    intrPrms.corepacConfig.corepacEventNum = 0U; /* NOT USED ? */
    intrPrms.corepacConfig.intVecNum        = intNum;

    osalRetVal = Osal_RegisterInterrupt(&intrPrms, &hwiHandle);
    appLogPrintf("[%s:%d] Osal_RegisterInterrupt intNum=%d osalRetVal=%d\n",__func__, __LINE__,intNum,osalRetVal);
    if(OSAL_INT_SUCCESS != osalRetVal)
    {
         appLogPrintf ("Osal_RegisterInterrupt fail \n");
    }else{
         appLogPrintf ("Osal_RegisterInterrupt fine \n");
    }
}
void initAllGpioisIntrrput(void)
{

#ifdef  GPIO0_2_5
	initGpioisIntrrput(GPIO_5_PIN_NUM);
	initGpioisIntrrput(GPIO_2_PIN_NUM);
#endif 

#ifdef GPIO_BANK1
	initGpioisIntrrput(GPIO_17_PIN_NUM);
	initGpioisIntrrput(GPIO_19_PIN_NUM);
#endif 


#ifdef  GPIO0_49_50
 	initGpioisIntrrput(GPIO_49_PIN_NUM);
 	initGpioisIntrrput(GPIO_50_PIN_NUM);
#endif 

}


void mcu30test_gpio_interrupt(void)
{
  //  int32_t i = 0; 
    gpio_pinmux();
    initAllGpioisIntrrput();
 	App_setupGpioMuxIr();



#if defined(GPIO_BANK1) && defined(GPIO0_2_5)  && defined(GPIO0_49_50) 
    appLogPrintf ("GPIO0_2_5 17 19 49 50 \n");
	register_isr_fun(176,&gpio_callback_isr_2);  
    register_isr_fun(177,&gpio_callback_isr_5); 
	 
    register_isr_fun(178,&gpio_callback_isr_17);
	register_isr_fun(179,&gpio_callback_isr_19); 

	register_isr_fun(180,&gpio_callback_isr_49);  
	register_isr_fun(181,&gpio_callback_isr_50); 
#elif  defined(GPIO0_2_5)
	register_isr_fun(176,&gpio_callback_isr_2);  
    register_isr_fun(177,&gpio_callback_isr_5); 
	
#elif defined(GPIO_BANK1)  
    appLogPrintf ("GPIO0_17 19 \n");
	register_isr_fun(178,&gpio_callback_isr_17);  
	register_isr_fun(179,&gpio_callback_isr_19); 
	
#elif  defined(GPIO0_49_50) 
    appLogPrintf ("GPIO0_49_50 \n");
	register_isr_fun(180,&gpio_callback_isr_49);  
	register_isr_fun(181,&gpio_callback_isr_50); 
#endif
  
}

3. The Pinmux configuration is correct. In separate tests, each group of GPIO interrupts were normal.

To simplify, I removed the other 6 GPIO interrupts.

Regards,

0 Brijesh Jadav over 1 year ago in reply to gg yang

TI__Guru**** 475345 points

hi gj y,

"1.The value of GPIO_INT_STAT register (0x600034 or 0x60005c) is 0."

This is important, if the GPIO module itself is not generating interrupt, then there will not be any ISR called for it. Can you please check first why this register is set to 0?

Regards,

Brijesh

0 gg yang over 1 year ago in reply to Brijesh Jadav

Expert 1190 points

Hi Brijesh

I saw the generation of gpio0_50 generates an interrupt and immediately reads the value of 0x600050, which is also 0, Has it been cleared by the system?

[MCU3_0] 92.445278 s: interrupt...GPIO_PIN_NUM 50
[MCU3_0] 92.445305 s: interrupt...GPIO_PIN_NUM 50

root@j721s2-evm:# devmem2 0x600034
/dev/mem opened.
Memory mapped at address 0xffff80f21000.
Read at address 0x00600034 (0xffff80f21034): 0x00000000
root@j721s2-evm:# devmem2 0x60005c
/dev/mem opened.
Memory mapped at address 0xffff9d98e000.
Read at address 0x0060005C (0xffff9d98e05c): 0x00000000

0 gg yang over 1 year ago in reply to Brijesh Jadav

Expert 1190 points

Hi Brijesh

The GPIO that can enter the interrupt processing function, with the corresponding bit of the GPIO_INT_STAT register being 1.

Unable to enter the GPIO of the interrupt processing function, the GPIO_INT_STAT register register bit with rising or falling edges is always 0

156.925797 s: read 600034 value is0x20,0x60005c value is 0x0
156.925823 s: interrupt...GPIO_PIN_NUM 5

#define GPIO0_2_5
#define GPIO_BANK1
#define GPIO0_49_50

I am confused why only one of the above three macro definitions can be opened, and its corresponding GPIO can enter an interrupt.

After entering an interrupt, its corresponding GPIO GPIO_INT_STAT register bit is 1, while opening all three macro definitions will only result in gpio0_ 49 gpio0_ 50 can enter the interrupt, while the GPIO_INT_STAT register bit is 1. Can't the other 4 GPIOs enter interrupts?

Regards,

+1 Brijesh Jadav over 1 year ago in reply to gg yang

TI__Guru**** 475345 points

Hi gj,

gg yang said:
I saw the generation of gpio0_50 generates an interrupt and immediately reads the value of 0x600050, which is also 0, Has it been cleared by the system?

Should not be. May be Linux is clearing it. I think the GPIO pin, GPIO0_50 can also be used as GPIO4_50, so instead of GPIO0, can you try using GPIO4? In pinmux register, you can select the GPIO to be used for this pin using VGPIO_SEL field and once you use GPIO4, you will need to configure GPIO4 module.

gg yang said:
Unable to enter the GPIO of the interrupt processing function, the GPIO_INT_STAT register register bit with rising or falling edges is always 0

This is a problem. If status here is not set, then there will not be any ISR. Please first check pinmux, and then see if GPIO4 can be used for these pins.

gg yang said:
I am confused why only one of the above three macro definitions can be opened, and its corresponding GPIO can enter an interrupt.

I am not really sure about it. Need to check in the code. May be there is some interdependency.

gg yang said:
After entering an interrupt, its corresponding GPIO GPIO_INT_STAT register bit is 1, while opening all three macro definitions will only result in gpio0_ 49 gpio0_ 50 can enter the interrupt, while the GPIO_INT_STAT register bit is 1. Can't the other 4 GPIOs enter interrupts?

Not sure exactly. May be there is some dependency. I would suggest to add one GPIO at a time and get it working.

Regards,

Brijesh

0 gg yang over 1 year ago in reply to Brijesh Jadav

Expert 1190 points

Brijesh Jadav said: Not sure exactly. May be there is some dependency. I would suggest to add one GPIO at a time and get it working

Only register gpio0_2 gpio0_5, gpio0_ 2 gpio0_5 can work. Then add gpio0_17, only gpio0_17 can enter interrupt processing,

but gpio0_2 gpio0_ 5 will not work properly, Continue adding gpio0_19, then only gpio0_17 gpio0_19 can work normally.

add gpio0_49, then only gpio0_49 can work normally. But gpio0_2 gpio0_5 gpio0_17 gpio0_1 19 cannot work.

0 Brijesh Jadav over 1 year ago in reply to gg yang

TI__Guru**** 475345 points

Hi gj y,

ok, so when you add gpio0_2, gpio0_5, they work fine, but when you add gpio0_17, they stop working? Is it correct understanding?

that's strange. Can you please check if there is any register change when you add gpio0_17? can you check if Bank interrupt is still enabled in the BINTEN register? This is required. Also please confirm there is no change in the pinmux for these pins.

Regards,

Brijesh

Processors

Processors forum

TDA4VE-Q1: Multiple GPIO input interrupts