Hello Sreenivasa,
You mentioned "It will remain high until the device has been put into CANUART mode and told to enter deep-sleep, where it is driven low to turn off the PMIC."
Regarding the above, is it only VDDSHV_CANUART that still needs to be powered in order to drive PMIC_LPM_EN0 low even when PMIC is off? For example, is it possible to keep PMIC_LPM_EN0 low even if we don't continue to supply 0.85V (or 0.75V) to VDD_CANUART?
(Concerned about not being able to keep the EN pin of PMIC low and the PMIC will unintentionally transition to the active state again)
By the way, we do not expect to use Partial IO mode.
(We do not assume that an event such as CAN Wakeup will start the system.)
We would like to decide
- Power the VDD_CANUART from 0.85V (or 0.75 V) of the PMIC output (common with power supplies such as VDD_core (=0.85 V or 0.75 V)),
Or
- VDD_CANUART can be supplied as a discrete external supply (to allow 0.75V to remain active even when PMIC off)
Best regards,
Ken
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