Connecting TMS320C6A8168 GPMC to TMS320C6746 HPI

Hi guys...

Any ideas on the above? I'm at a standstill on this issue and would like to get some direction.

Thanks again.

Ockie Van Schalkwyk said:

Seeing that the HPI has a 16-bit multiplexed address and data bus, it follows that we should use the GPMC in this mode as well (refer to SPRUGX9, Fig. 9.2).

No, that's not the case.  In particular please look at Figure 1 "TMS320C62x/C67x/C64x (HPI16) EMIF to HPI Interface Block Diagram". Notice that EA[4:3] (address lines) are being connected to HCNTL[1:0] and EA2 is connected to HHWIL.  In other words, the address you write to in the GPMC space will dictate which mode of operation the HPI enters.

Ockie Van Schalkwyk said:

I would appreciate some guidance on the above connection scheme (perhaps there is a more applicable Application Note that I've missed?).

A couple things that have changed:

1. The ARDY pin from the 64x EMIF is now a WAIT pin on the GPMC, so the inverter shown in spra536 should no longer be necessary.
2. The mapping of addresses to address pins is something that is device specific.  In this case we need to consult the DM8168 TRM.  Specifically see Table 9-2 "GPMC Pin Multiplexing Options".  Specifically, in the 16-bit mode pin GPMC_A0 is not used and GPMC_A1 represents the lowest bit of the 16-bit address.  In other words GPMC_A1 must be connected to HHWIL.

Also, here's a slight modification I would recommend.  In spra536 some very low address pins (EA[4:3]) are connected to HCNTL[1:0].  I recommend using some higher address pins for that purpose.  That will give you an entire block of memory addresses that will map to the various commands which will might improve your throughput a bit in that you'd be able to use incrementing DMA transfers, etc.

Brad

Hi Brad

Thank you for the explanation and suggestions :)

Would you be willing to review my GPMC <=> HPI connections after the schematic design of this portion has been completed? I appreciate your time and help on this!

Kind regards

Ockie

Sure, post a snippet and I'll have a look.

Hi Brad

Could you please have a look at my GPMC - HPI connection? I've uploaded a snippet from the relevant section in the schematic.0434.GPMC_HPI_Connection_2011-08-26.pdf

For now we are using the C6A8168 DDR3 (Rev.E) EVM and connecting its GPMC to the HPI of a LogicPD OMAP-L138 SOM (though, in our final application we will be using a TMS320C6746 DSP instead of the OMAP-L138). The GPMC interface is also connected to an FPGA (not shown).

Thank you and regards

Ockie

Ockie,

I specifically mentioned that GPMC_A[1] needs to be connected to UHPI_HHWIL -- but you didn't do that!  Please make that change...

I'm concerned about the timing of the HR/W signal on the UHPI.  The data sheet requires a 5ns setup time relative to the falling edge of /HSTROBE.  In the case of a read, /HSTROBE will be controlled by the /GPMC_OE signal.  In other words, the UHPI's HR/W signal must correctly indicate read/write 5ns before /HDS2 transitions low.  Right now you have /GPMC_OE going through an inverter and so that will not work...  I think you should connect an address pin to HR/W.  That way the GPMC address to which you write will specify whether you're doing a read or a write on the UHPI.  The address will be valid before even the chip select is asserted so we will easily meet the timing requirements this way.

Use GPMC_DIR instead of GPMC_OE and you can get rid of the inverter.

Brad

Hi Brad

I sure listened to your advice, but maybe I misinterpreted it slightly.... apologies for that :)

Looking at the "Multiplexed Address Data 16-Bit Device" column of Table 9.2 GPMC Pin Multiplexing Options (document SPRUGX9), the GPMC_A[1] output is listed as "Not Used" (which I interpreted as "not functioning" or "not defined"), as it is clearly being multiplexed with GPMC_D[0]. It is my understanding that with UHPI_HHWIL connected to GPMC_D[0], the GPMC's lowest address bit (GPMC_A[1]) will be latched in as control information on UHPI_HHWIL during the GPMC's addressing phase - or am I missing something here?

For the rest of it, am I correct in summarizing your suggestions as follows:

(a) connect UHPI_HR/W to GPMC_A[??];

(b) connect UHPI_/HDS2 to GPMC_DIR.

Thanks again!

Ockie

Ockie Van Schalkwyk said:

Looking at the "Multiplexed Address Data 16-Bit Device" column of Table 9.2 GPMC Pin Multiplexing Options (document SPRUGX9), the GPMC_A[1] output is listed as "Not Used" (which I interpreted as "not functioning" or "not defined"), as it is clearly being multiplexed with GPMC_D[0].

I just opened that document and do not see what you are saying...  Here's a snippet:

 The pin GPMC_A[1] corresponds to address bit 0 of the 16-bit device.  In other words, GPMC_A[1] tells which whether you are on an even or odd 16-bit word, which is why it should be hooked to HHWIL.

Also, you mention multiplexing of the data and address lines.  To be clear you must configure the GPMC for non-multiplexed operation so no multiplexing applies here.

Ockie Van Schalkwyk said:

(a) connect UHPI_HR/W to GPMC_A[??];

(b) connect UHPI_/HDS2 to GPMC_DIR

Yep.  I'll me traveling M-W next week so I may not be able to reply again.

Hi Brad

Apologies for my late reply. I was stuck on the idea of interfacing to the UHPI using a multiplexed address / data bus, as I thought this would give the lowest overhead on the Integra processor's side -- but I see the error of my ways now!

For the sake of completeness, please see my latest connection diagram (with GPMC_A[1] connected to HHWIL) : 6038.EVM_Interface_2011-09-06.pdf

Thank you again and regards

-Ockie