AM6442: Adding DP83848 as PHY for RMII in U-Boot

s k

Part Number: AM6442

Hello,

we are trying to connect the Ethernet PHY DP83848 to our custom board with an AM6442. The hardware of the custom board was validated with the BOOTP functionality in RBL, which worked properly. We are using SDK 09.00.00.03 and our Ethernet hardware is connected for RMII2 and MDIO. The PHYAD is 0x10.

We have made several changes in the U-Boot directory of the SDK listed below:

am64x_evm_a53_defconfig

CONFIG_MULTI_DTB_FIT=n
CONFIG_SPL_MULTI_DTB_FIT=n
CONFIG_PHY_TI_GENERIC=y

k3-am642-r5-sk.dts

mdio1_pins_default: mdio1-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x015c, PIN_OUTPUT, 4) /* (Y6) PRG1_MDIO0_MDC.MDIO0_MDC */
			AM64X_IOPAD(0x0158, PIN_INPUT, 4) /* (AA6) PRG1_MDIO0_MDIO.MDIO0_MDIO */
		>;
	};

&main_pmx0 {
	bootph-pre-ram;
	main_uart0_pins_default: main-uart0-pins-default {
		bootph-pre-ram;
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0238, PIN_INPUT, 0)		/* (B16) UART0_CTSn */
			AM64X_IOPAD(0x023c, PIN_OUTPUT, 0)		/* (A16) UART0_RTSn */
			AM64X_IOPAD(0x0230, PIN_INPUT, 0)		/* (D15) UART0_RXD */
			AM64X_IOPAD(0x0234, PIN_OUTPUT, 0)		/* (C16) UART0_TXD */
		>;
	};

	main_uart1_pins_default: main-uart1-pins-default {
		bootph-pre-ram;
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0248, PIN_INPUT, 0)		/* (D16) UART1_CTSn */
			AM64X_IOPAD(0x024c, PIN_OUTPUT, 0)		/* (E16) UART1_RTSn */
			AM64X_IOPAD(0x0240, PIN_INPUT, 0)		/* (E15) UART1_RXD */
			AM64X_IOPAD(0x0244, PIN_OUTPUT, 0)		/* (E14) UART1_TXD */
		>;
	};

	main_mmc0_pins_default: main-mmc0-pins-default {
		bootph-pre-ram;
		pinctrl-single,pins = <
			AM64X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0)	/* (B25) MMC0_CLK */
			AM64X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0)	/* (B27) MMC0_CMD */
			AM64X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0)	/* (A26) MMC0_DAT0 */
			AM64X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0)	/* (E25) MMC0_DAT1 */
			AM64X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0)	/* (C26) MMC0_DAT2 */
			AM64X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0)	/* (A25) MMC0_DAT3 */
			AM64X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0)	/* (E24) MMC0_DAT4 */
			AM64X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0)	/* (A24) MMC0_DAT5 */
			AM64X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0)	/* (B26) MMC0_DAT6 */
			AM64X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0)	/* (D25) MMC0_DAT7 */
		AM64X_IOPAD(0x01b0, PIN_INPUT, 0)		/* (C25) MMC0_DS */
			>;
	};

	main_usb0_pins_default: main-usb0-pins-default {
		bootph-pre-ram;
		pinctrl-single,pins = <
			AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
		>;
	};

	mdio1_pins_default: mdio1-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x015c, PIN_OUTPUT, 4) /* (Y6) PRG1_MDIO0_MDC.MDIO0_MDC */
			AM64X_IOPAD(0x0158, PIN_INPUT, 4) /* (AA6) PRG1_MDIO0_MDIO.MDIO0_MDIO */
		>;
	};

    rmii2_pins_default: rmii2-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x013c, PIN_INPUT, 5) /* (U10) PRG1_PRU1_GPO13.RMII2_CRS_DV */
			AM64X_IOPAD(0x0108, PIN_INPUT, 5) /* (W11) PRG1_PRU1_GPO0.RMII2_RXD0 */
			AM64X_IOPAD(0x010c, PIN_INPUT, 5) /* (V11) PRG1_PRU1_GPO1.RMII2_RXD1 */
			AM64X_IOPAD(0x0118, PIN_INPUT, 5) /* (W12) PRG1_PRU1_GPO4.RMII2_RX_ER */
			AM64X_IOPAD(0x0134, PIN_OUTPUT, 5) /* (AA10) PRG1_PRU1_GPO11.RMII2_TXD0 */
			AM64X_IOPAD(0x0138, PIN_OUTPUT, 5) /* (V10) PRG1_PRU1_GPO12.RMII2_TXD1 */
			AM64X_IOPAD(0x0144, PIN_OUTPUT, 5) /* (Y11) PRG1_PRU1_GPO15.RMII2_TX_EN */
			AM64X_IOPAD(0x00e0, PIN_INPUT, 5) /* (U14) PRG1_PRU0_GPO10.RMII_REF_CLK */
		>;
	};

	ospi0_pins_default: ospi0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
			AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
			AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
			AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
			AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
			AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
			AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
			AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
			AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
			AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
			AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
		>;
	};
};

&cpsw3g {
	pinctrl-names = "default";
	pinctrl-0 = <&mdio1_pins_default &rmii2_pins_default>;
};

&cpsw_port1 {
	phy-mode = "rmii";
	phy-handle = <&cpsw3g_phy0>;
};

&cpsw3g_mdio {
	cpsw3g_phy0: ethernet-phy@0 {
		status = "okay";
		reg = <16>;
	};
};

k3-am642-sk.dts

&main_pmx0 {
	main_mmc0_pins_default: main-mmc0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0)	/* (B25) MMC0_CLK */
			AM64X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0)	/* (B27) MMC0_CMD */
			AM64X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0)	/* (A26) MMC0_DAT0 */
			AM64X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0)	/* (E25) MMC0_DAT1 */
			AM64X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0)	/* (C26) MMC0_DAT2 */
			AM64X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0)	/* (A25) MMC0_DAT3 */
			AM64X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0)	/* (E24) MMC0_DAT4 */
			AM64X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0)	/* (A24) MMC0_DAT5 */
			AM64X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0)	/* (B26) MMC0_DAT6 */
			AM64X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0)	/* (D25) MMC0_DAT7 */
			AM64X_IOPAD(0x01b0, PIN_INPUT, 0)		    /* (C25) MMC0_DS   */
		>;
	};

	main_uart0_pins_default: main-uart0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
			AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
			AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
			AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
		>;
	};

	main_usb0_pins_default: main-usb0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
		>;
	};

	main_i2c1_pins_default: main-i2c1-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
			AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
		>;
	};

	mdio1_pins_default: mdio1-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x015c, PIN_OUTPUT, 4) /* (Y6) PRG1_MDIO0_MDC.MDIO0_MDC */
			AM64X_IOPAD(0x0158, PIN_INPUT, 4) /* (AA6) PRG1_MDIO0_MDIO.MDIO0_MDIO */
		>;
	};

    rmii2_pins_default: rmii2-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x013c, PIN_INPUT, 5) /* (U10) PRG1_PRU1_GPO13.RMII2_CRS_DV */
			AM64X_IOPAD(0x0108, PIN_INPUT, 5) /* (W11) PRG1_PRU1_GPO0.RMII2_RXD0 */
			AM64X_IOPAD(0x010c, PIN_INPUT, 5) /* (V11) PRG1_PRU1_GPO1.RMII2_RXD1 */
			AM64X_IOPAD(0x0118, PIN_INPUT, 5) /* (W12) PRG1_PRU1_GPO4.RMII2_RX_ER */
			AM64X_IOPAD(0x0134, PIN_OUTPUT, 5) /* (AA10) PRG1_PRU1_GPO11.RMII2_TXD0 */
			AM64X_IOPAD(0x0138, PIN_OUTPUT, 5) /* (V10) PRG1_PRU1_GPO12.RMII2_TXD1 */
			AM64X_IOPAD(0x0144, PIN_OUTPUT, 5) /* (Y11) PRG1_PRU1_GPO15.RMII2_TX_EN */
			AM64X_IOPAD(0x00e0, PIN_INPUT, 5) /* (U14) PRG1_PRU0_GPO10.RMII_REF_CLK */
		>;
	};

	ospi0_pins_default: ospi0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
			AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
			AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
			AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
			AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
			AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
			AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
			AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
			AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
			AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
			AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
		>;
	};

	main_ecap0_pins_default: main-ecap0-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
		>;
	};
	main_wlan_en_pins_default: main-wlan-en-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */
		>;
	};

	main_com8_ls_en_pins_default: main-com8-ls-en-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */
		>;
	};

	main_wlan_pins_default: main-wlan-pins-default {
		pinctrl-single,pins = <
			AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */
		>;
	};
};

&cpsw3g {
	pinctrl-names = "default";
	pinctrl-0 = <&rmii2_pins_default>;
};

&cpsw_port1 {
	phy-mode = "rmii";
	phy-handle = <&cpsw3g_phy0>;
};

&cpsw3g_mdio {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mdio1_pins_default>;

	cpsw3g_phy0: ethernet-phy@0 {
		status = "okay";
		reg = <16>;
	};
};

k3-am642-sk-u-boot.dtsi

&main_mmc0_pins_default {
	bootph-pre-ram;
};

&cpsw3g {
	reg = <0x0 0x8000000 0x0 0x200000>,
	      <0x0 0x43000200 0x0 0x8>;
	reg-names = "cpsw_nuss", "mac_efuse";
	/delete-property/ ranges;
	pinctrl-0 = <&mdio1_pins_default &rmii2_pins_default>;
	bootph-pre-ram;

	cpsw-phy-sel@04044 {
		compatible = "ti,am64-phy-gmii-sel";
		reg = <0x0 0x43004044 0x0 0x8>;
		bootph-pre-ram;
		rmii-clock-ext;
	};

	ethernet-ports {
		bootph-pre-ram;
	};
};

&cpsw_port1 {
	bootph-pre-ram;
};

&cpsw_port2 {
	status = "disabled";
};

&rmii2_pins_default {
	bootph-pre-ram;
};

&mdio1_pins_default {
	bootph-pre-ram;
};

&cpsw3g_phy0 {
	bootph-pre-ram;
};

Once we compiled everything, flashed the files and are in U-Boot, we get the following output for the commands:

=> mii device
MII devices: 'ethernet@8000000port@1'
Current device: 'ethernet@8000000port@1'

=> mii info
PHY 0x10: OUI = 0x80017, Model = 0x09, Rev = 0x00, 100baseT, FDX

=> mdio read ethernet@8000000port@1 0
Reading from bus ethernet@8000000port@1
PHY at address 10:
0 - 0x3100
=> mdio read ethernet@8000000port@1 1
Reading from bus ethernet@8000000port@1
PHY at address 10:
1 - 0x786d
=> mdio read ethernet@8000000port@1 2
Reading from bus ethernet@8000000port@1
PHY at address 10:
2 - 0x2000
=> mdio read ethernet@8000000port@1 3
Reading from bus ethernet@8000000port@1
PHY at address 10:
3 - 0x5c90
=> mdio read ethernet@8000000port@1 4
Reading from bus ethernet@8000000port@1
PHY at address 10:
4 - 0x1e1
=> mdio read ethernet@8000000port@1 5
Reading from bus ethernet@8000000port@1
PHY at address 10:
5 - 0xcde1
=> mdio read ethernet@8000000port@1 6
Reading from bus ethernet@8000000port@1
PHY at address 10:
6 - 0xf
=> mdio read ethernet@8000000port@1 7
Reading from bus ethernet@8000000port@1
PHY at address 10:
7 - 0x2801
=> mdio read ethernet@8000000port@1 8
Reading from bus ethernet@8000000port@1
PHY at address 10:
8 - 0x0
=> mdio read ethernet@8000000port@1 9
Reading from bus ethernet@8000000port@1
PHY at address 10:
9 - 0x0
=> mdio read ethernet@8000000port@1 10
Reading from bus ethernet@8000000port@1
PHY at address 10:
16 - 0x15
=> mdio read ethernet@8000000port@1 11
Reading from bus ethernet@8000000port@1
PHY at address 10:
17 - 0x0
=> mdio read ethernet@8000000port@1 12
Reading from bus ethernet@8000000port@1
PHY at address 10:
18 - 0x2c00
=> mdio read ethernet@8000000port@1 13
Reading from bus ethernet@8000000port@1
PHY at address 10:
19 - 0x0
=> mdio read ethernet@8000000port@1 14
Reading from bus ethernet@8000000port@1
PHY at address 10:
20 - 0x0
=> mdio read ethernet@8000000port@1 15
Reading from bus ethernet@8000000port@1
PHY at address 10:
21 - 0x0
=> mdio read ethernet@8000000port@1 16
Reading from bus ethernet@8000000port@1
PHY at address 10:
22 - 0x100
=> mdio read ethernet@8000000port@1 17
Reading from bus ethernet@8000000port@1
PHY at address 10:
23 - 0x21
=> mdio read ethernet@8000000port@1 18
Reading from bus ethernet@8000000port@1
PHY at address 10:
24 - 0x0
=> mdio read ethernet@8000000port@1 19
Reading from bus ethernet@8000000port@1
PHY at address 10:
25 - 0x8030

=> mii dump 10 0
0.     (3100)                 -- PHY control register --
  (8000:0000) 0.15    =     0     reset
  (4000:0000) 0.14    =     0     loopback
  (2040:2000) 0. 6,13 =   b01    speed selection = 100 Mbps
  (1000:1000) 0.12    =     1     A/N enable
  (0800:0000) 0.11    =     0     power-down
  (0400:0000) 0.10    =     0     isolate
  (0200:0000) 0. 9    =     0     restart A/N
  (0100:0100) 0. 8    =     1     duplex = full
  (0080:0000) 0. 7    =     0     collision test enable
  (003f:0000) 0. 5- 0 =     0     (reserved)

=> ping 192.168.1.1
link up on port 1, speed 100, full duplex
*** ERROR: `ipaddr' not set
ping failed; host 192.168.1.1 is not alive
=> setenv ipaddr 192.168.1.111
=> ping 192.168.1.1
link up on port 1, speed 100, full duplex
Using ethernet@8000000port@1 device
ARP Retry count exceeded; starting again
ping failed; host 192.168.1.1 is not alive

Our goal is to have the PHY properly integrated so that a ping is possible. Please let us know where in our configuration we have an error or if you need more information.

Thanks for your help in advance!

Sam

over 2 years ago

0 Pekka Varis over 2 years ago

TI__Mastermind 27050 points

The PHY expert for AM6x is out on vacation and will be back later this week. But as couple first checks, did you try to ping 192.168.1.111 from 192.168.1.1 ? Do you have a sniffer like profishark to see if there is any traffic coming out of the AM6442 when you try to ping 192.168.1.1? Also if you further boot Linux does Ethernet work?

0 s k over 2 years ago in reply to Pekka Varis

Prodigy 10 points

Thank you for the reply,

we have made several attempts to ping. Above you can see the attempt to reach the host with IP 192.168.1.1 from our board, which was assigned with IP 192.168.1.111.
We have also used Wireshark and found that there is no traffic coming from the board to the host. (DHCP nor BOOTP request, also checked for the MAC).
Linux can not be booted on the board because we need NFS and TFTP which depend on the RMII interface.

Kindly,

Sam

0 s k over 2 years ago in reply to s k

Prodigy 10 points

In addition to my last answer,

when the primary boot mode is set to Ethernet, we can identify the BOOTP packets sent by the RBL using Wireshark.

(These are answered by our DHCP/BOOTP server but this answer cannot be processed correctly by our board yet. Unfortunately we currently do not know how to debug the RBL to see why this is the case in this step.)

Kindly,

Sam

0 Schuyler Patton over 2 years ago in reply to s k

TI__Mastermind 40130 points

Hi,

Since you are seeing the BOOTP response from your server on wireshark the next step is to look at the MAC statistics of the port and see if the device is seeing any packets.

Please look for this register in the TRM for the device.

12.3.3.1.174.1 CPSW0_RXGOODFRAMES Register (Offset = 3A000h) [reset = 0h ]

This register is the start of MAC statistics for the CPSW. There are several registers related to packet receive. Please read them using the u-boot md.l command to see if any packets are being received.

Best Regards,

Schuyler

0 Schuyler Patton over 2 years ago in reply to Schuyler Patton

TI__Mastermind 40130 points

Hi,

I apologize, after re-reading the post only through ethernet boot, I am assuming that you are able to load u-boot. How is it loaded?

Best Regards,

Schuyler

0 s k over 2 years ago in reply to Schuyler Patton

Prodigy 10 points

Hey,

we load U-Boot via the UART interface using the UART boot mode. Once we have loaded U-Boot, we have the problem described above that we cannot successfully execute the ping.
My last comment regarding the RBL and BOOTP requests should clarify that the hardware is configured correctly and the problem is related to U-Boot and the DTS config.

Kindly,

Sam

0 Schuyler Patton over 2 years ago in reply to s k

TI__Mastermind 40130 points

Hi,

I would like to make sure we are aligned on the setup. For the moment since U-Boot is loading over UART lets look at the problem in this context without RBL. Since you are seeing the packets on Wireshark this proves out the TX path, now there is a need prove the BOOTP response packets at least make to the MAC RX statistics.

With the UART U-Boot loaded please try these commands:

setenv autoload n (this tells U-Boot only to do DHCP and not start a tftp session)

md.l 0x0803a000 (lets look at the RX frames good count prior to running dhcp, I see 0 and what I expect after a boot)

dhcp (this sends BOOTP packets)

I see several BOOTP broadcast messages, after the 4th message my board is bound to an ip address.

Now when I look at the following address to look at RX good frames count I see a non zero number.

md.l 0x0803a000 (here I see 5 RX frames)

When I run dhcp again this number goes up. If this number is 0 on your board that says the BOOTP responses are not making it to the MAC interface. This could be a DTS issue or a HW issue but narrows down the direction to look at initially.

Best Regards,

Schuyler

0 s k over 2 years ago in reply to Schuyler Patton

Prodigy 10 points

Hi,

Thank you for your reply.

Sure, let's focus on loading U-Boot via UART. I believe there was a small misunderstanding here. After we load U-Boot via UART and then send a DHCP request or ping, we don't see any messages in Wireshark. This means that TX (SOC->PC) is not working.

If I execute the commands you mentioned in U-Boot, I get the following output:

=> setenv autoload n
=> md.l 0x0803a000
0803a000: 00000003 00000003 00000000 00000000  ................
0803a010: 00000000 00000000 00000000 00000000  ................
0803a020: 00000000 00000000 00000000 00000000  ................
0803a030: 0000040e 00000000 00000000 00000000  ................
0803a040: 00000000 00000000 00000000 00000000  ................
0803a050: 00000000 00000000 00000000 00000000  ................
0803a060: 00000000 00000000 00000000 00000000  ................
0803a070: 00000000 00000003 00000000 00000000  ................
0803a080: 0000040e 00000000 00000000 00000000  ................
0803a090: 00000000 00000000 00000000 00000000  ................
0803a0a0: 00000000 00000000 00000000 00000000  ................
0803a0b0: 00000000 00000000 00000003 0000040e  ................
0803a0c0: 00000000 00000000 00000000 00000000  ................
0803a0d0: 00000000 00000000 00000000 00000000  ................
0803a0e0: 00000000 00000000 00000000 00000000  ................
0803a0f0: 00000000 00000000 00000000 00000000  ................
=> dhcp
link up on port 1, speed 100, full duplex
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
BOOTP broadcast 5
BOOTP broadcast 6
BOOTP broadcast 7
BOOTP broadcast 8
BOOTP broadcast 9
BOOTP broadcast 10
BOOTP broadcast 11
BOOTP broadcast 12
BOOTP broadcast 13
BOOTP broadcast 14
BOOTP broadcast 15
BOOTP broadcast 16
BOOTP broadcast 17

Abort
=> md.l 0x0803a000
0803a000: 00000014 00000014 00000000 00000000  ................
0803a010: 00000000 00000000 00000000 00000000  ................
0803a020: 00000000 00000000 00000000 00000000  ................
0803a030: 00001b08 00000000 00000000 00000000  ................
0803a040: 00000000 00000000 00000000 00000000  ................
0803a050: 00000000 00000000 00000000 00000000  ................
0803a060: 00000000 00000000 00000000 00000000  ................
0803a070: 00000000 00000014 00000000 00000000  ................
0803a080: 00001b08 00000000 00000000 00000000  ................
0803a090: 00000000 00000000 00000000 00000000  ................
0803a0a0: 00000000 00000000 00000000 00000000  ................
0803a0b0: 00000000 00000000 00000014 00001b08  ................
0803a0c0: 00000000 00000000 00000000 00000000  ................
0803a0d0: 00000000 00000000 00000000 00000000  ................
0803a0e0: 00000000 00000000 00000000 00000000  ................
0803a0f0: 00000000 00000000 00000000 00000000  ................
=>

It appears that I'm receiving 17 RX good frames, but there are no TX good frames.

Do you have any idea what might be causing this?

Best Regards

Sam

0 Schuyler Patton over 2 years ago in reply to s k

TI__Mastermind 40130 points

Hi,

This means that the TX packets are not leaving the MAC. Since there are not any TX packets we need to review the clock and the TX enable signal. There are a couple of possibilities, one is the pin mux is not correct and the other is the CLK is not correct. I support the SW side of the interface so I will need to pull in a HW apps team member. The HW apps will be asking for a scope capture of the CLK and TX enable I imagine.

Best Regards,

Schuyler

Processors

Processors forum

AM6442: Adding DP83848 as PHY for RMII in U-Boot