uboot nor flash boot patch

hi i modify some uboot code for 8148 nor flash boot

diff --git a/arch/arm/cpu/arm_cortexa8/ti81xx/lowlevel_init.S b/arch/arm/cpu/arm_cortexa8/ti81xx/lowlevel_init.S
index 5de3519..390ce29 100644
--- a/arch/arm/cpu/arm_cortexa8/ti81xx/lowlevel_init.S
+++ b/arch/arm/cpu/arm_cortexa8/ti81xx/lowlevel_init.S
@@ -347,13 +347,14 @@ ocmc0_wait0:
        ldr r5, cm_alwon_ocmc_0_clkctrl_addr
        mov r2, #0x2
        str r2, [r5]
-       /* wait for gpmc enable to settle */
+       /* wait for gpmc enable to settle */
 ocmc0_wait1:
        ldr r2, [r5]
        ands r2, r2, #0x00030000
        cmp r2, #0
        bne ocmc0_wait1

+#ifdef CONFIG_TI816X
        /**** enable ocmc 1 ****/
        /* CLKSTCTRL */
        ldr r5, cm_alwon_ocmc_1_clkstctrl_addr
@@ -376,6 +377,7 @@ ocmc1_wait1:
        cmp r2, #0
        bne ocmc1_wait1

+#endif
 nor_init_start:
        /* gpmc init */
        bl  cpy_nor_gpmc_code /* copy nor gpmc init code to sram */
@@ -398,11 +400,15 @@ s_init_start:
 cm_alwon_ocmc_0_clkstctrl_addr:
        .word CM_ALWON_OCMC_0_CLKSTCTRL
 cm_alwon_ocmc_0_clkctrl_addr:
-       .word CM_ALWON_OCMC_0_CLKCTRL
+       .word CM_ALWON_OCMC_0_CLKCTRL
+#ifdef CONFIG_TI816X
+
 cm_alwon_ocmc_1_clkstctrl_addr:
        .word CM_ALWON_OCMC_1_CLKSTCTRL
+
 cm_alwon_ocmc_1_clkctrl_addr:
        .word CM_ALWON_OCMC_1_CLKCTRL
+#endif
 SRAM_STACK:
        .word (SRAM0_START + SRAM0_SIZE - SRAM_GPMC_STACK_SIZE)
 #else

maybe it will be useful