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DM365 digital video output in BT.656 mode

Stefano54155
Prodigy 70 points

I'm working on a proprietary board based on DM365. I'm trying to output digital BT.656 720P signal to interface with THS8134B video D/A converter.

I see getting out clock and data with an oscilloscope but it seems that clock is twice data frequency.

I'm using internal 74.25 clock setting SYS_VPSS_CLKCTL at 0x38.

THS8134 samples data at clock rising edge so, working on DCLK I can get correct timings, but when I enable YCCCTL.R656 all DCLK settings are ignored.

Obviously without setting YCCCTL.R656 there aren't embedded sync.

Output of color bar on a vga monitor has correct resolution but wrong image.

Also..

There is a note at page 45 of sprufg9c.pdf: "Note that this mode operates correctly only when the pixel clock frequency is half of the VENC clock."

What does it means?

Thanks in advance

 

  • 0
    TI__Expert 4685 points

    What standard you want to drive to  THS8134B?

    See if section 4.5.4.1 of VPBE user guide helps.

    There is a reference for non-standard mode:-

    http://processors.wiki.ti.com/index.php/How_to_program_VPBE_YCC8_digital_out

  • 0 in reply to Nagabhushana
    Prodigy 70 points

    Sorry for my late answer but I'm back to work only today.

    I need to drive THS8134B in YCC8 mode (8 bit YCbCr) using ITU-R BT.656 standard.

    My goal is to display in 720p format (1280x720).

    I'm using internal 74.25 clock setting SYS_VPSS_CLKCTL at 0x38, THS8134 samples data at clock rising edge so, working on DCLK register I can get correct timings, but when I enable YCCCTL.R656 all DCLK register settings are ignored.

    Obviously without setting YCCCTL.R656 there aren't embedded sync.

    The note at page 45 of sprufg9c.pdf says: "Note that this mode operates correctly only when the pixel clock frequency is half of the VENC clock."

    How can I satisfy this condition in BT.656 mode if as soon as I enable BT.656 mode all DCLK register settings are ignored?

    Thanks.