Part Number: TDA4VM
I used SDK8.4. In my custom board, I used the MT53E1G32D2FW-046 AUT:B as LPDDR4. But the board boot failed due to timeout during frequency handshake.
The boot log is shown as follows:
U-Boot SPL 2021.01 (Sep 06 2023 - 03:07:54 +0000)
Model: Texas Instruments K3 J721E SoC
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
SYSFW ABI: 3.1 (firmware rev 0x0008 '8.4.1--v08.04.01 (Jolly Jellyfi')
EEPROM not available at 0x50, trying to read at 0x51
Reading on-board EEPROM at 0x51 failed 1
k3_lpddr4_freq_update: received freq change req: req type = 1, req no. = 0 , instance = 0
U-Boot SPL 2021.01 (Sep 06 2023 - 03:23:02 +0000)
Model: Texas Instruments K3 J721E SoC
0 0
- 0 0 'i2c@42120000'
- found
dm_i2c_probe: bus='i2c@42120000', address 50, ret=1
EEPROM not available at 0x50, trying to read at 0x51
0 0
- 0 0 'i2c@42120000'
- found
dm_i2c_probe: bus='i2c@42120000', address 51, ret=1
Reading on-board EEPROM at 0x51 failed 1
Board: J721EX-PM1-SOM rev E2
SYSFW ABI: 3.1 (firmware rev 0x0008 '8.4.1--v08.04.01 (Jolly Jellyfi')
0 0
- 0 0 'i2c@42120000'
- found
dm_i2c_probe: bus='i2c@42120000', address 50, ret=1
EEPROM not available at 0x50, trying to read at 0x51
0 0
- 0 0 'i2c@42120000'
- found
dm_i2c_probe: bus='i2c@42120000', address 51, ret=1
Reading on-board EEPROM at 0x51 failed 1
size=x, ptr=8, limit=56ea4: 41cdca9c
0 -1
0 0
- -1 -1 'esm'
- -1 -1 'ringacc@2b800000'
- -1 -1 'wkup_vtm@42040000'
- -1 -1 'esm@700000'
- not found
0 0
- -1 0 'pinctrl@4301c000'
- found
fdtdec_get_int: #power-domain-cells: x (2)
power_domain_get_by_index(dev=41c87188, power_domain=41c85abc)
fdtdec_get_int: #power-domain-cells: x (2)
ti_power_domain_of_xlate(power_domain=41c85abc, id=154)
power_domain_on(power_domain=41c85abc)
ti_power_domain_on(pd=41c85abc, id=0)
ti_lpsc_transition: transitioning psc:1, lpsc:0 to 3
psc_read: 0x103 from 42000a00
clk_set_defaults(wkup_vtm@42040000)
clk_set_default_parents: could not read assigned-clock-parents for 41c87188
ofnode_read_prop: assigned-clock-rates: <not found>
ofnode_read_u32_index: vdd-supply-2: x (34)
size=x, ptr=4, limit=56ea8: 41cdcaa4
0 -1
0 0
- -1 -1 'tps659413a@48'
- -1 -1 'tps65917@58'
- not found
0 -1
0 0
- -1 -1 'wkup-i2c0-pins-default'
- -1 -1 'mcu-fss0-hpb0-pins-default'
- -1 -1 'mcu-fss0-ospi0-pins-default'
- -1 0 'wkup_uart0_pins_default'
- found
0 1
- -1 -1 'wkup-i2c0-pins-default'
- -1 -1 'mcu-fss0-hpb0-pins-default'
- -1 -1 'mcu-fss0-ospi0-pins-default'
- -1 0 'wkup_uart0_pins_default'
- -1 -1 'mcu_uart0_pins_default'
- -1 -1 'wkup-gpio-pins-default'
- -1 -1 'mcu-fss0-ospi1-pins-default'
- -1 2 'main_uart0_pins_default'
- -1 1 'main_usbss0_pins_default'
- found
0 2
- -1 -1 'wkup-i2c0-pins-default'
- -1 -1 'mcu-fss0-hpb0-pins-default'
- -1 -1 'mcu-fss0-ospi0-pins-default'
- -1 0 'wkup_uart0_pins_default'
- -1 -1 'mcu_uart0_pins_default'
- -1 -1 'wkup-gpio-pins-default'
- -1 -1 'mcu-fss0-ospi1-pins-default'
- -1 2 'main_uart0_pins_default'
- found
0 3
- -1 -1 'wkup-i2c0-pins-default'
- -1 -1 'mcu-fss0-hpb0-pins-default'
- -1 -1 'mcu-fss0-ospi0-pins-default'
- -1 0 'wkup_uart0_pins_default'
- -1 -1 'mcu_uart0_pins_default'
- -1 -1 'wkup-gpio-pins-default'
- -1 -1 'mcu-fss0-ospi1-pins-default'
- -1 2 'main_uart0_pins_default'
- -1 1 'main_usbss0_pins_default'
- -1 -1 'main_mmc1_pins_default'
- -1 -1 'main-i2c0-pins-default'
- not found
0 0
- -1 0 'pinctrl@4301c000'
- found
clk_set_defaults(wkup-i2c0-pins-default)
clk_set_default_parents: could not read assigned-clock-parents for 41c8606c
ofnode_read_prop: assigned-clock-rates: <not found>
clk_set_defaults(tps659413a@48)
clk_set_default_parents: could not read assigned-clock-parents for 41c864bc
ofnode_read_prop: assigned-clock-rates: <not found>
0 -1
0 0
- -1 -1 'buck12'
- -1 -1 'smps12'
- -1 -1 'smps3'
- -1 -1 'smps4'
- -1 -1 'smps5'
- -1 -1 'ldo1'
- -1 -1 'ldo2'
- -1 -1 'ldo3'
- -1 -1 'ldo4'
- -1 -1 'ldo5'
- not found
0 0
- -1 0 'pinctrl@4301c000'
- found
ofnode_read_u32_index: regulator-min-microvolt: x (600000)
ofnode_read_u32_index: regulator-max-microvolt: x (900000)
ofnode_read_u32_index: regulator-init-microvolt: (not found)
ofnode_read_u32_index: regulator-min-microamp: (not found)
ofnode_read_u32_index: regulator-max-microamp: (not found)
ofnode_read_bool: regulator-always-on: true
ofnode_read_bool: regulator-boot-on: true
ofnode_read_u32_index: regulator-ramp-delay: (not found)
ofnode_find_subnode: regulator-state-mem: <none>
clk_set_defaults(buck12)
clk_set_default_parents: could not read assigned-clock-parents for 41c86538
ofnode_read_prop: assigned-clock-rates: <not found>
ofnode_read_u32_index: ti,default-opp-2: (not found)
OF: ** translation for device wkup_vtm@42040000 **
OF: bus is default (na=2, ns=2) on bus@28380000
OF: parent bus is default (na=2, ns=2) on bus@100000
OF: walking ranges...
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: with offset: u
OF: parent bus is default (na=2, ns=2) on
OF: walking ranges...
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: default map, cp=x, s=x, da=x
OF: with offset: u
OF: reached root node
pmic_reg_read: reg=e priv->trans_len:1i2c_xfer: 2 messages
i2c_xfer: chip=0x48, len=0x1
i2c_xfer: chip=0x48, len=0x1
, value=37, ret=0
pmic_reg_read: reg=5 priv->trans_len:1i2c_xfer: 2 messages
i2c_xfer: chip=0x48, len=0x1
i2c_xfer: chip=0x48, len=0x1
, value=2b, ret=0
pmic_reg_write: reg=e, value=41 priv->trans_len:1i2c_xfer: 1 messages
i2c_xfer: chip=0x48, len=0x2
, ret=0
size=x, ptr=d0, limit=56f78: 41cdcaa8
0 -1
0 0
- -1 -1 'memorycontroller@0298e000'
- not found
0 0
- -1 0 'pinctrl@4301c000'
- found
fdtdec_get_int: #power-domain-cells: x (2)
fdtdec_get_int: #power-domain-cells: x (2)
power_domain_get_by_index(dev=41c87d08, power_domain=41c85ab4)
fdtdec_get_int: #power-domain-cells: x (2)
ti_power_domain_of_xlate(power_domain=41c85ab4, id=47)
power_domain_on(power_domain=41c85ab4)
ti_power_domain_on(pd=41c85ab4, id=15)
ti_lpsc_transition: transitioning psc:0, lpsc:15 to 3
psc_read: 0x100 from 400a3c
psc_write: 0x103 to 400a3c
psc_write: 0x1 to 400120
psc_read: 0x1 from 400128
psc_read: 0x0 from 400128
psc_read: 0x1f03 from 40083c
power_domain_get_by_index(dev=41c87d08, power_domain=41c85ab4)
fdtdec_get_int: #power-domain-cells: x (2)
fdtdec_get_int: #power-domain-cells: x (2)
ti_power_domain_of_xlate(power_domain=41c85ab4, id=90)
power_domain_on(power_domain=41c85ab4)
ti_power_domain_on(pd=41c85ab4, id=14)
ti_lpsc_transition: transitioning psc:0, lpsc:14 to 3
psc_read: 0x100 from 400a38
psc_write: 0x103 to 400a38
psc_write: 0x1 to 400120
psc_read: 0x0 from 400128
psc_read: 0x1f03 from 400838
clk_set_defaults(memorycontroller@0298e000)
clk_set_default_parents: could not read assigned-clock-parents for 41c87d08
ofnode_read_prop: assigned-clock-rates: <not found>
k3_ddrss_probe(dev=41c87d08)
k3_ddrss_ofdata_to_priv(dev=41c87d08)
OF: ** translation for device memorycontroller@0298e000 **
OF: bus is default (na=2, ns=2) on
OF: reached root node
OF: ** translation for device memorycontroller@0298e000 **
OF: bus is default (na=2, ns=2) on
OF: reached root node
power_domain_get_by_index(dev=41c87d08, power_domain=41cdcab8)
fdtdec_get_int: #power-domain-cells: x (2)
ti_power_domain_of_xlate(power_domain=41cdcab8, id=47)
power_domain_get_by_index(dev=41c87d08, power_domain=41cdcac4)
fdtdec_get_int: #power-domain-cells: x (2)
fdtdec_get_int: #power-domain-cells: x (2)
ti_power_domain_of_xlate(power_domain=41cdcac4, id=90)
fdtdec_get_int: #clock-cells: x (2)
ti_clk_of_xlate(clk=41cdcad0, args_count=2 [0]=47 [1]=2)
clk_request(dev=41c85e34, clk=41cdcad0)
fdtdec_get_int: #clock-cells: x (2)
fdtdec_get_int: #clock-cells: x (2)
ti_clk_of_xlate(clk=41cdcaf0, args_count=2 [0]=30 [1]=9)
clk_request(dev=41c85e34, clk=41cdcaf0)
ofnode_read_u32_index: ti,ddr-freq0: x (27500000)
ofnode_read_u32_index: ti,ddr-freq1: x (1066500000)
ofnode_read_u32_index: ti,ddr-freq2: x (1066500000)
ofnode_read_u32_index: ti,ddr-fhs-cnt: x (10)
ofnode_read_bool: ti,ecc-enable: false
k3_ddrss_power_on(ddrss=41cdcaa8)
power_domain_on(power_domain=41cdcab8)
ti_power_domain_on(pd=41cdcab8, id=15)
power_domain_on(power_domain=41cdcac4)
ti_power_domain_on(pd=41cdcac4, id=14)
ofnode_read_u32_index: vtt-supply: (not found)
LPDDR4_Probe: PASS
LPDDR4_Init: PASS
ofnode_read_u32_array: ti,ctl-data: fdtdec_get_int_array: ti,ctl-data
get_prop_check_min_len: ti,ctl-data
ofnode_read_u32_array: ti,pi-data: fdtdec_get_int_array: ti,pi-data
get_prop_check_min_len: ti,pi-data
ofnode_read_u32_array: ti,phy-data: fdtdec_get_int_array: ti,phy-data
get_prop_check_min_len: ti,phy-data
clk_set_rate(clk=41cdcad0, rate=27500000)
clk_get_rate(clk=41cda5c0)
clk_get_parent_rate(clk=41cda5c0)
clk_get_parent(clk=41cda5c0)
clk_get_rate(clk=41cd9f00)
clk_get_parent_rate(clk=41cd9f00)
clk_get_parent(clk=41cd9f00)
clk_get_rate(clk=41cd7440)
clk_get_parent_rate(clk=41cd7440)
clk_get_parent(clk=41cd7440)
clk_set_rate(clk=41cda5c0, rate=27500000)
clk_get_parent_rate(clk=41cda5c0)
clk_get_parent(clk=41cda5c0)
clk_get_rate(clk=41cda5c0)
clk_get_parent_rate(clk=41cda5c0)
clk_get_parent(clk=41cda5c0)
ti_clk_set_rate: clk=hsdiv0_16fft_main_12_hsdivout0_clk, div=1, rate=27500000, new_rate=20000000, diff=7500000
clk_get_parent_rate(clk=41cda5c0)
clk_get_parent(clk=41cda5c0)
clk_set_rate(clk=41cda5c0, rate=47500000)
clk_get_parent_rate(clk=41cda5c0)
clk_get_parent(clk=41cda5c0)
clk_get_rate(clk=41cda5c0)
clk_get_parent_rate(clk=41cda5c0)
clk_get_parent(clk=41cda5c0)
ti_clk_set_rate: Using better rate 20000000 that gives diff 7500000
--->>> LPDDR4 Initialization is in progress ... <<<---
k3_lpddr4_freq_update: received freq change req: req type = 1, req no. = 0 , instance = 0
clk_set_rate(clk=41cdcad0, rate=1066500000)
clk_get_rate(clk=41cda5c0)
clk_get_parent_rate(clk=41cda5c0)
clk_get_parent(clk=41cda5c0)
clk_set_rate(clk=41cda5c0, rate=1066500000)
clk_get_parent_rate(clk=41cda5c0)
clk_get_parent(clk=41cda5c0)
clk_get_rate(clk=41cda5c0)
clk_get_parent_rate(clk=41cda5c0)
clk_get_parent(clk=41cda5c0)
ti_clk_set_rate: clk=hsdiv0_16fft_main_12_hsdivout0_clk, div=1, rate=1066500000, new_rate=20000000, diff=1046500000
ti_clk_set_rate: propagating rate change to parent, rate=1066500000.
clk_get_parent(clk=41cda5c0)
ti_clk_set_rate: pll_tgt=2133000000, rate=1066500000, div=2
clk_set_rate(clk=41cd9f00, rate=2133000000)
clk_get_parent_rate(clk=41cd9f00)
clk_get_parent(clk=41cd9f00)
ti_pll_clk_set_rate(clk=41cd9f00, rate=2133000000)
clk_get_parent_rate(clk=41cd9f00)
clk_get_parent(clk=41cd9f00)
ti_pll_clk_set_rate: pre-frac-calc: rate=2133000000, parent_freq=20000000, plld=20, pllm=2133
ti_pll_clk_set_rate: pllm=106, plld=1, pllfm=10905191, parent_freq=20000000
clk_set_rate(clk=41cda5c0, rate=1066500000)
clk_get_parent_rate(clk=41cda5c0)
clk_get_parent(clk=41cda5c0)
clk_get_rate(clk=41cd9f00)
clk_get_parent_rate(clk=41cd9f00)
clk_get_parent(clk=41cd9f00)
clk_get_rate(clk=41cda5c0)
clk_get_parent_rate(clk=41cda5c0)
clk_get_parent(clk=41cda5c0)
Timeout during frequency handshake
