SK-AM62A-LP: PMIC_LPM_EN0 connection to PMIC

KenF

Part Number: SK-AM62A-LP

Hello Experts,

PMIC_LPM_EN0 can be switched for "GPIO3" and "ENABLE" of PMIC. What is the design intent?

Best regards,
Ken

over 2 years ago

0 Kallikuppa Sreenivasa over 2 years ago

TI__Guru**** 197199 points

Hello Ken,

Thank you for the query.

I assume you are asking about the EVM implementation.

The GPIO has the below functions.

I am not sure on the implementation.

Help me understand the use case for me to reassign.

Regards,

Sreenivasa

0 KenF over 2 years ago in reply to Kallikuppa Sreenivasa

TI__Expert 7150 points

Hello Sreenivasa,

I meant this switch.

Best regards,
Ken

0 Kallikuppa Sreenivasa over 2 years ago in reply to KenF

TI__Guru**** 197199 points

Hello Ken,

Thank you.

This chooses one of the two PMIC functionalities - Enable or Sleep.

Can you elaborate your query.

Regards,

Sreenivasa

0 KenF over 2 years ago in reply to Kallikuppa Sreenivasa

TI__Expert 7150 points

Hello Sreenivasa,

Does it switch I/O only + DDR low power mode and Partial IO low power mode?

Best regards,
Ken

0 Kallikuppa Sreenivasa over 2 years ago in reply to KenF

TI__Guru**** 197199 points

Hello Ken,

Thank you.

Please refer the 62A TRM section as below.

and the PMIC data sheet. section

I am not sure how the PMIC implements the sleepmode and not sure if additional supply is required since the reset logic uses VCC_3V3_MAIN..

You could start a thread to reach out to the PMIC team or if you do not have any additional queries, i can reassign the same to the PMIC team with the only note that the PMIC team will have to read through the thread before answering probably causing some delay.

Regards,

Sreenivasa

0 KenF over 2 years ago in reply to Kallikuppa Sreenivasa

TI__Expert 7150 points

Hello Sreenivasa,

Thank you. We would like to know why board designer added the switch. Can you check with the board designer?

Best regards,
Ken

+1 Kallikuppa Sreenivasa over 2 years ago in reply to KenF

TI__Guru**** 197199 points

Hello Ken,

Thank you.

The provision was added on the starter kit to be able demonstrate partial IO and deep sleep mode.

I assume you are interested in understating how the PMCI functions with these 2 pins configured - let me know if understand correctly.

Regards,

Sreenivasa

+1 Kallikuppa Sreenivasa over 2 years ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 197199 points

Hello Ken,

Just in case you have not had a chance to look at the below

httpsHello Ken, ://www.ti.com/lit/wp/sprad41/sprad41.pdf

(+) TPS6593-Q1: what is the meaning of IO+DDR and Partial IO low power mode - Power management forum - Power management - TI E2E support forums

IO+DDR low power mode has all the power rails disabled except BUCK4 and BUCK5, which supply the 1.8V IO domain and DDR rails. Partial IO low power mode has all the power rails of the PMIC disabled.

From the AM62Ax Sitara Processors Technical Reference Manual (Rev. A), In Partial I/O, I/O pins and small logics in the CANUART I/O Bank are active, and the rest of the SoC is turned off. The user can use the I/O pins to aggregate multiple I/O wakeup events and toggle PMIC_LPM_EN pin to enable PMIC or discrete power solution when an I/O wakeup event is triggered. The information on the I/O wakeup event is logged in the MMR in the CANUART I/O bank and helps the software to distinguish between cold boot and wakeup to respond to the wakeup event faster.

There is currently no explanation of the I/O + DDR power mode in the AM62A TRM to explain the implementation on from the processor perspective.

Regards,

Sreenivasa

Processors

Processors forum

SK-AM62A-LP: PMIC_LPM_EN0 connection to PMIC