AM623: GPMC CycleTime counter

John Booth64

Part Number: AM623

What events cause the GPMC CYCLETIME counter to reset and start counting? I am seeing an occasional corruption of GPMC_AD6 on a burst read. The corruption tends to occur when the bit was set on the previous cycle. Mostly I have seen this on the third burst. By my calculations I should have adequate setup margin, so the only thing I can think of is the SoC has a different view of the CYCLETIME counter than I am expecting.

Thanks,

John

over 1 year ago

0 Bin Liu over 1 year ago

TI__Guru**** 167271 points

Hi John,

I am routing your query to our GPMC expert for comments.

0 Kallikuppa Sreenivasa over 1 year ago

TI__Guru**** 188529 points

Hello John,

Could you please share additional information on the setup you are using and the tests done.

Regards,

Sreenivasa

0 John Booth64 over 1 year ago in reply to Kallikuppa Sreenivasa

Prodigy 130 points

I have the following GPMC config settings:

GPMC_CONFIG1=0x79401200
GPMC_CONFIG2=0x00030500
GPMC_CONFIG3=0x11010100
GPMC_CONFIG4=0x03018522
GPMC_CONFIG5=0x02040405
GPMC_CONFIG6=0x82010000
GPMC_CONFIG7=0x00000F50

The GPMC endpoint is a FPGA. We are burst reading from memory in the FPGA. We have an embedded logic analyzer in the FPGA to compare the read value versus the value put onto the bus.

John

0 Kallikuppa Sreenivasa over 1 year ago in reply to John Booth64

TI__Guru**** 188529 points

Hello John,

Thank you.

Please describe the GPMC interface you are using between the SoC and the FPGA.

Regards,

Sreenivasa

0 John Booth64 over 1 year ago in reply to Kallikuppa Sreenivasa

Prodigy 130 points

Synchronous 100 MHz Mulitplexed Address Data 16-Bit Device. Hopefully the Config registers provided previously can be used to answer any additional questions about the GPMC.

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AM623: GPMC CycleTime counter