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TDA4AH-Q1: SysConfig - SerDes part not generated

Scott Brown
Prodigy 190 points
Part Number: TDA4AH-Q1
Other Parts Discussed in Thread: SYSCONFIG, TDA4VH

Hi TI,

I'm using SysConfig to configure the J784s4, and am wondering if the SysConfig software tool may have an issue on SerDes part.

When using the tool to configure pins like AR24 or AT7 on SerDes, it does not generated anything in the generated files.
The only thing on SerDes found is in the csv file with lines on power domains.

The software version used is SysConfig 1.17.0+3128.

If this is not an issue, can we be provided with an example of the SerDes configuration pinmux ?

Kind Regards,
Scott

  • 0
    TI__Mastermind 48243 points

    Hello Scott,

    To understand the issue better, Can you tell us what SerDes instance you are planning to use in your configuration?

    The possible pins for SerDes instances are fixed as described in the Chapter 6.3.20 of the TDA4VH datasheet. Can you check if this is what you see in the generated files.

    Thanks.

  • 0 in reply to Praveen Rao
    TI__Guru** 112475 points

    Hi Scott,

    The PinMux configuration is required only for pads/balls that have multiple IP lines muxed on them. The configuration is done using Memory-Mapped PADCONF registers using MuxModes.

    SerDes lines are on fixed pins without any additional functionality. So, these do not need any additional pinmux configuration, and do not have any associated PADCONFIG registers. SysConfig Tool therefore does not generate any output for these.

    egards

    Suman

  • 0 in reply to Praveen Rao
    Prodigy 190 points

    Hi Praveen,

    Thanks for your reply!

    In the block CPSW9X, we tried to use SerDes pins on SGMII5/6/7/8 signals, but nothing appeared in the generated files, is it normal ?

    How are we supposed to deal with it in that case?

  • 0 in reply to Suman Anna
    Prodigy 190 points

    Hi Suman,

    Thanks for your reply as well.

    So something like AR20 is in our CPSW9X block, set on signal SGMII7

    However nothing appears in the pinmux generated files. How does this get configured?

    Thanks,
    Scott

  • 0 in reply to Scott Brown
    TI__Mastermind 48243 points

    Hello Scott,

    Scott Brown said:
    However nothing appears in the pinmux generated files. How does this get configured?

    As previously noted, the SERDES pin are dedicated and do not need any pinmux configuration.

    Scott Brown said:
    In the block CPSW9X, we tried to use SerDes pins on SGMII5/6/7/8 signals, but nothing appeared in the generated files, is it normal ?

    We are not able to understand your question here. Can you rephrase what the issue is? How are you configuring the SGMII? What reference software you are using for this?

    Thanks.

  • 0 in reply to Praveen Rao
    Prodigy 190 points

    Hi Praveen,

    So for example, AR20 SERDES2_TX2_N has Mux mode 0 and 1 - however there are no PADCONF registers. So this isn't configurable? How would we pick Mux Mode 0 or 1?


    Whereas something like AR8 doesn't require configuration as there is no Mux mode, and the choice between HYP_RXN0 and PCIE1_RXN0 is a SerDes configuration?

    We are using SysConfig to configure the following, however nothing appears for them in the generated files. Is this normal?

    J784S4_pinmux_USB_SSRX_SSTX_SERDES0

    Thanks,
    Scott

  • 0 in reply to Scott Brown
    TI__Mastermind 48243 points

    Hello Scott,

    I'll have to get back on this after consulting our dev team. Give us a day or so.

    Thanks.

  • +1 in reply to Scott Brown
    TI__Guru 65140 points

    Hi Scott,

    Scott Brown said:
    So for example, AR20 SERDES2_TX2_N has Mux mode 0 and 1 - however there are no PADCONF registers. So this isn't configurable? How would we pick Mux Mode 0 or 1?

    We have CTRL_MMR registers for all Serdes Lane controls, which select the IP for the SerDes Lane.
    There is no PAD configuration for SerDes IPs selection, as mentioned above SerDes lines are on fixed pins without any additional functionality.
    Input to SerDes will be configurable, which is above CTRL_MMR configuration of SerDes Lanes.

    Example:
    On SerDes2 Lane2 we can select SGMII7 or SGMII1 (either MAC Port-7 or MAC Port-1), which is selected using above CTRL_MMR registers.
    Output from SerDes2 Lane2 is fixed which is TX2P, TX2N, RX2P, RX2N lines.

    Please refer to SOC Register details for more information.

    Based on IP select SerDes Lane Pins functions for that IP (MAC Port/PCIe/HyperLink/USB).

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 190 points

    Hi Sudheer,

    Thanks for your response. This answered my question!

    Kind regards,

    Scott