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[FAQ] AM625: eMMC timing

Juergen Elst
Prodigy 170 points

Part Number: AM625

Hello,

we are currently working on a SOM based on the AM62x. 

I am qualifying the MMC0 interface connected to a EMMC (SDINBDG4-8G-XI2). I have checked the datasheet of the AM62x and found this:

 

I only found MMC0 timing conditions for SDIO mode instead of EMMC mode.

At the AM64x datasheet i clearly find some conditions regarding the eMMCPHY, like those:

The input slew rate is clearly different from the AM64x to AM62x. 

Are there no such specifications for the AM62x?

  • +1
    TI__Guru 63605 points

    AM62x supports three eMMC data transfer modes, Legacy SDR, High Speed SDR, and HS200. The AM62x Timing Conditions table defines input slew rate for Legacy SDR and High Speed SDR for both 1.8V and 3.3V operation. Input slew rate was defined for these two modes because training is not used to find the data valid window. Input slew rate was not defined for HS200 because training is used to find the data valid window.

    The min slew rate defined in the AM64x Electrical Characteristics table is not related to timing requirements. This min slew rate parameter is defined to constrain the max time allowed for the signal to transition between logic levels. This parameter limits the input buffer shoot-through current duration and is only defined to ensure long-term device reliability. The slew rates parameters defined in the respective Timing Condition tables should be used to constrain timing.

    Regards,
    Paul