This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Our customer connects AM62x DSS parallel interface to TFP410 on their custom board.
Can the delay time between PCLK and each other output signal (VSYNC, HSYNC, DATA[23:0], DE) be adjusted by register settings?
Best regards,
Daisuke
Hello Daisuke,
Thank you for the query.
Please help us understand the use case.
Series resistors are recommended.
As i understand, we do not have provision to adjust individual signal delay.
Regards,
Sreenivasa